LTC3729L-6 Datasheet, PDF (10/28 Pages) Linear Technology – PolyPhase, Synchronous Step-Down Switching Regulator

LTC3729L-6
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OPERATIO (Refer to Functional Diagram)
Main Control Loop
The LTC3729L-6 uses a constant frequency, current mode
step-down architecture. During normal operation, the top
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the main current
comparator, I1, resets the RS latch. The peak inductor
current at which I1 resets the RS latch is controlled by the
voltage on the I_TH pin, which is the output of the error
amplifier EA. The differential amplifier, A1, produces a
signal equal to the differential voltage sensed across the
output capacitor but re-references it to the internal signal
ground (SGND) reference. The EAIN pin receives a portion
of this voltage feedback signal at the DIFFOUT pin which
is compared to the internal reference voltage by the EA.
When the load current increases, it causes a slight de-
crease in the EAIN pin voltage relative to the 0.6V refer-
ence, which in turn causes the I_TH voltage to increase until
the average inductor current matches the new load cur-
rent. After the top MOSFET has turned off, the bottom
MOSFET is turned on for the rest of the period.
The top MOSFET drivers are biased from floating boot-
strap capacitor C_B, which normally is recharged during
each off cycle through an external Schottky diode. When
V_IN decreases to a voltage close to V_OUT, however, the loop
may enter dropout and attempt to turn on the top MOSFET
continuously. A dropout detector detects this condition
and forces the top MOSFET to turn off for about 400ns
every 10th cycle to recharge the bootstrap capacitor.
The main control loop is shut down by pulling Pin 1 (RUN/
SS) low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor C_SS. When
C_SS reaches 1.5V, the main control loop is enabled with the
I_TH voltage clamped at approximately 30% of its maximum
value. As C_SS continues to charge, I_TH is gradually re-
leased allowing normal operation to resume. When the
RUN/SS pin is low, all LTC3729L-6 functions are shut
down. If V_OUT has not reached 70% of its nominal value
when C_SS has charged to 4.1V, an overcurrent latchoff can
be invoked as described in the Applications Information
section.
Low Current Operation
The LTC3729L-6 operates in a continuous, PWM control
mode. The resulting operation at low output currents
optimizes transient response at the expense of substantial
negative inductor current during the latter part of the
period. The level of ripple current is determined by the
inductor value, input voltage, output voltage, and fre-
quency of operation.
Frequency Synchronization
The phase-locked loop allows the internal oscillator to be
synchronized to an external source via the PLLIN pin. The
output of the phase detector at the PLLFLTR pin is also the
DC frequency control input of the oscillator that operates
over a 260kHz to 550kHz range corresponding to a DC
voltage input from 0V to 2.4V. When locked, the PLL aligns
the turn on of the top MOSFET to the rising edge of the
synchronizing signal. When PLLIN is left open, the PLLFLTR
pin goes low, forcing the oscillator to minimum frequency.
The internal master oscillator runs at a frequency twelve
times that of each controller’s frequency. The PHASMD
pin determines the relative phases between the internal
controllers as well as the CLKOUT signal as shown in
Table␣ 1. The phases tabulated are relative to zero phase
being defined as the rising edge of the top gate (TG1)
driver output of controller 1.
Table 1.
V_PHASMD
GND
Controller 2
180°
CLKOUT
60°
OPEN
180°
90°
INTV_CC
240°
120°
The CLKOUT signal can be used to synchronize additional
power stages in a multiphase power supply solution
feeding a single, high current output or separate outputs.
Input capacitance ESR requirements and efficiency losses
are substantially reduced because the peak current drawn
from the input capacitor is effectively divided by the
number of phases used and power loss is proportional to
the RMS current squared. A two stage, single output
voltage implementation can reduce input path power loss
by 75% and radically reduce the required RMS current
rating of the input capacitor(s).
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