LTC3729L-6 Datasheet, PDF (19/28 Pages) Linear Technology – PolyPhase, Synchronous Step-Down Switching Regulator

LTC3729L-6
APPLICATIO S I FOR ATIO
center frequency f_O. A voltage applied to the PLLFLTR pin
of 1.2V corresponds to a frequency of approximately
400kHz. The nominal operating frequency range of the
LTC3729L-6 is 260kHz to 550kHz.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, ∆f_H, is equal to the capture range, ∆f_C:
∆f_H = ∆f_C = ±0.5 f_O (260kHz-550kHz)
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin. A simplified block
diagram is shown in Figure 7.
If the external frequency (f_PLLIN) is greater than the oscil-
lator frequency f_0SC, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency
is less than f_0SC, current is sunk continuously, pulling
down the PLLFLTR pin. If the external and internal fre-
quencies are the same but exhibit a phase difference, the
current sources turn on for an amount of time correspond-
ing to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor C_LP holds the voltage. The
LTC3729L-6 PLLIN pin must be driven from a low imped-
ance source such as a logic gate located close to the pin.
When using multiple LTC3729L-6’s for a phase-locked
system, the PLLFLTR pin of the master oscillator should
be biased at a voltage that will guarantee the slave
oscillator(s) ability to lock onto the master’s frequency. A
DC voltage of 1.6V to 1.7V applied to the master oscillator’s
PLLFLTR pin is recommended in order to meet this
requirement. The resultant operating frequency will be
approximately 500kHz.
The loop filter components (C_LP, R_LP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C_LP and R_LP determine how fast the loop
acquires lock. Typically R_LP =10kΩ and C_LP is 0.01µF to
0.1µF.
EXTERNAL
OSC
2.4V
PHASE
DETECTOR
PLLIN
DIGITAL
PHASE/
FREQUENCY
50k
DETECTOR
R_LP
10k
C_LP
PLLFLTR
OSC
3729L-6 F07
Figure 7. Phase-Locked Loop Block Diagram
Minimum On-Time Considerations
Minimum on-time t_ON(MIN) is the smallest time duration
that the LTC3729L-6 is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
t_ON(MIN)
<
V_OUT
V_IN(f₎
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3729L-6 will begin to skip
cycles resulting in nonconstant frequency operation. The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
The minimum on-time for the LTC3729L-6 is generally
less than 200ns. However, as the peak sense voltage
decreases the minimum on-time gradually increases. This
is of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre-
spondingly larger current and voltage ripple.
If an application can operate close to the minimum on-
time limit, an inductor must be chosen that has a low
enough inductance to provide sufficient ripple amplitude
to meet the minimum on-time requirement. As a general
rule, keep the inductor ripple current of each phase equal
to or greater than 15% of I_OUT(MAX)/N at V_IN(MAX).
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