LTC3736-2 Datasheet, PDF (23/28 Pages) Linear Technology – Dual 2-Phase, No RSENSE Synchronous Controller with Output Tracking

LTC3736-2
APPLICATIO S I FOR ATIO
increased by decreasing C_C. The output voltage settling
behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C_LOAD).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3736-2. These items are illustrated in the layout dia-
gram of Figure 13. Figure 14 depicts the current wave-
forms present in the various branches of the 2-phase dual
regulator.
1) The power loop (input capacitor, MOSFETs, inductor,
output capacitor) of each channel should be as small as
possible and isolated as much as possible from the
power loop of the other channel. Ideally, the drains of
the P- and N-channel FETs should be connected close
to one another with an input capacitor placed across
the FET sources (from the P-channel source to the N-
channel source) right at the FETs. It is better to have
two separate, smaller valued input capacitors (e.g.,
two 10µF—one for each channel) than it is to have a
single larger valued capacitor (e.g., 22µF) that the
channels share with a common connection.
2) The signal and power grounds should be kept separate.
The signal ground consists of the feedback resistor
dividers, I_TH compensation networks and the SGND pin.
The power grounds consist of the (–) terminal of the
input and output capacitors and the source of the N-
channel MOSFET. Each channel should have its own
LTC3736EGN-2
1
SW1
SENSE1^{+ 24}
2
IPRG1
23
PGND
3
V_FB1
4
I_TH1
5
IPRG2
22
BG1
21
SYNC/FCB
20
TG1
6
19
PLLLPF PGND
7
SGND
18
TG2
8
V_IN
9
TRACK
17
RUN/SS
16
BG2
10
V_FB2
11
I_TH2
12
PGOOD
15
PGND
SENSE2^{+ 14}
13
SW2
C_OUT1
V_OUT1
L1
MN1 MP1
C_VIN1
C_VIN
C_VIN2
MN2
V_IN
MP2
L2
C_OUT2
BOLD LINES INDICATE HIGH CURRENT PATHS
V_OUT2
37362 F13
Figure 13. LTC3736-2 Layout Diagram
power ground for its power loop (as described above
in item 1). The power grounds for the two channels
should connect together at a common point. It is most
important to keep the ground paths with high switch-
ing currents away from each other.
The PGND pins on the LTC3736-2 IC should be shorted
together and connected to the common power ground
connection (away from the switching currents).
3) Put the feedback resistors close to the V_FB pins. The
trace connecting the top feedback resistor (R_B) to the
output capacitor should be a Kelvin trace. The I_TH
compensation components should also be very close
to the LTC3736-2.
4) The current sense traces (SENSE⁺ and SW) should be
Kelvin connections right at the P-channel MOSFET
source and drain.
5) Keep the switch nodes (SW1, SW2) and the gate driver
nodes (TG1, TG2, BG1, BG2) away from the small-
signal components, especially the opposite channel’s
feedback resistors, I_TH compensation components,
and the current sense pins (SENSE⁺ and SW).
37362fa
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