LTC3736-2 Datasheet, PDF (17/28 Pages) Linear Technology – Dual 2-Phase, No RSENSE Synchronous Controller with Output Tracking

LTC3736-2
APPLICATIO S I FOR ATIO
capacitor current requirement. Increasing the output cur-
rent drawn from the other controller will actually decrease
the input RMS ripple current from its maximum value. The
out-of-phase technique typically reduces the input
capacitor’s RMS ripple current by a factor of 30% to 70%
when compared to a single phase power supply solution.
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle (V_OUT)/(V_IN). To
prevent large voltage transients, a low ESR capacitor sized
for the maximum RMS current of one channel must be
used. The maximum RMS capacitor current is given by:
[^{( )( )}] ^CIN
Required
I_RMS
≈
I_MAX
V_IN
V_OUT
1/2
V_IN – V_OUT
This formula has a maximum at V_IN = 2V_OUT, where I_RMS
= I_OUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design. Due to the high operating frequency of the
LTC3736-2, ceramic capacitors can also be used for C_IN.
Always consult the manufacturer if there is any question.
The benefit of the LTC3736-2 2-phase operation can be
calculated by using the equation above for the higher power
controller and then calculating the loss that would have
resulted if both controller channels switched on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s ESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the
dual controller design. Also, the input protection fuse re-
sistance, battery resistance, and PC board trace resistance
losses are also reduced due to the reduced peak currents
in a 2-phase system. The overall benefit of a multiphase
design will only be fully realized when the source imped-
ance of the power supply/battery is included in the effi-
ciency testing. The sources of the P-channel MOSFETs
should be placed within 1cm of each other and share a
common C_IN(s). Separating the sources and C_IN may pro-
duce undesirable voltage and current resonances at V_IN.
A small (0.1µF to 1µF) bypass capacitor between the chip
V_IN pin and ground, placed close to the LTC3736-2, is also
suggested. A 10Ω resistor placed between C_IN (C1) and
the V_IN pin provides further isolation between the two
channels.
The selection of C_OUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering. The
output ripple (∆V_OUT) is approximated by:
∆V_OUT
⎛
≈ I_{RIPPLE⎝⎜}ESR
+
1
8fC_OUT
⎞
⎠⎟
where f is the operating frequency, C_OUT is the output
capacitance and I_RIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since I_RIPPLE increases with input voltage.
Setting Output Voltage
The LTC3736-2 output voltages are each set by an external
feedback resistor divider carefully placed across the out-
put, as shown in Figure 5. The regulated output voltage is
determined by:
V_OUT
=
0.6V
•
⎛
⎝⎜¹⁺
R_B
R_A
⎞
⎠⎟
To improve the frequency response, a feedforward capaci-
tor, C_FF, may be used. Great care should be taken to route
the V_FB line away from noise sources, such as the inductor
or the SW line.
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