LTC3736-2 Datasheet, PDF (19/28 Pages) Linear Technology – Dual 2-Phase, No RSENSE Synchronous Controller with Output Tracking

APPLICATIO S I FOR ATIO
V_OUT1
V_OUT2
LTC3736-2
V_OUT1
V_OUT2
TIME
(7b) Coincident Tracking
TIME
37362 F07b,c
(7c) Ratiometric Tracking
Figures 7b and 7c. Two Different Modes of Output Voltage Tracking
For coincident tracking,
t_SS2
=
t_SS1
•
V_OUT2F
V_OUT1F
where V_OUT1F and V_OUT2F are the final, regulated values of
V_OUT1 and V_OUT2. V_OUT1 should always be greater than
V_OUT2 when using the TRACK pin. If no tracking function
is desired, then the TRACK pin may be tied to V_IN. How-
ever, in this situation there would be no (internal nor
external) soft-start on V_OUT2.
Phase-Locked Loop and Frequency Synchronization
The LTC3736-2 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the external P-
channel MOSFET of controller 1 to be locked to the rising
edge of an external clock signal applied to the SYNC/FCB
pin. The turn-on of controller 2’s external P-channel
MOSFET is thus 180 degrees out of phase with the
external clock. The phase detector is an edge sensitive
digital type that provides zero degrees phase shift
between the external and internal oscillators. This type of
phase detector does not exhibit false lock to harmonics of
the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relation-
ship between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to SYNC/
FCB, is shown in Figure 8 and specified in the Electrical
Characteristics table. Note that the LTC3736-2 can only be
synchronized to an external clock whose frequency is within
range of the LTC3736-2’s internal VCO, which is nominally
200kHz to 1MHz. This is guaranteed, over temperature and
variations, to be between 300kHz and 750kHz. A simplified
block diagram is shown in Figure 9.
If the external clock frequency is greater than the internal
oscillator’s frequency, f_OSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f_OSC, current is sunk continuously, pulling down the
1400
1200
1000
800
600
400
200
0
0
0.5
1
1.5
2 2.4
PLLLPF PIN VOLTAGE (V)
37362 F08
Figure 8. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
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