LTC3736-1 Datasheet, PDF (22/28 Pages) Linear Technology – Dual 2-Phase, No RSENSE Synchronous Controller with Spread Spectrum

LTC3736-1
APPLICATIO S I FOR ATIO
at the FETs. It is better to have two separate, smaller valued
input capacitors (e.g., two 10µF—one for each channel)
than it is to have a single larger valued capacitor (e.g.,
22µF) that the channels share with a common connection.
2) The signal and power grounds should be kept separate.
The signal ground consists of the feedback resistor divid-
ers, I_TH compensation networks and the SGND pin.
The power grounds consist of the (–) terminal of the input
and output capacitors and the source of the N-channel
MOSFET. Each channel should have its own power ground
for its power loop (as described in (1) above). The power
grounds for the two channels should connect together at
a common point. It is most important to keep the ground
paths with high switching currents away from each other.
The PGND pins on the LTC3736-1 IC should be shorted
together and connected to the common power ground
connection (away from the switching currents).
3) Put the feedback resistors close to the V_FB pins. The
trace connecting the top feedback resistor (R_B) to the
output capacitor should be a Kelvin trace. The I_TH compen-
sation components should also be very close to the
LTC3736-1.
4) The current sense traces (SENSE⁺ and SW) should be
Kelvin connections right at the P-channel MOSFET source
and drain.
5) Keep the switch nodes (SW1, SW2) and the gate driver
nodes (TG1, TG2, BG1, BG2) away from the small-signal
components, especially the opposite channels feedback
resistors, I_TH compensation components and the current
sense pins (SENSE⁺ and SW).
V_IN
R_IN
+
C_IN
MP1
MN1
L1
V_OUT1
+
C_OUT1
22
MP2
MN2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH
L2
V_OUT2
+
C_OUT2
Figure 12. Branch Current Waveforms
R_L1
R_L2
37361 F12
37361f