LTC3736-1 Datasheet, PDF (12/28 Pages) Linear Technology – Dual 2-Phase, No RSENSE Synchronous Controller with Spread Spectrum

LTC3736-1
U
OPERATIO (Refer to Functional Diagram)
The FREQ pin can be floated, tied to V_IN or tied to SGND to
select 550kHz, 750kHz or 300kHz respectively.
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to main-
tain low output ripple voltage.
Dropout Operation
When the input supply voltage (V_IN) decreases towards
the output voltage, the rate of change of the inductor
current while the external P-channel MOSFET is on (ON
cycle) decreases. This reduction means that the P-channel
MOSFET will remain on for more than one oscillator cycle
if the inductor current has not ramped up to the threshold
set by the EAMP on the I_TH pin. Further reduction in the
input supply voltage will eventually cause the P-channel
MOSFET to be turned on 100%; i.e., DC. The output
voltage will then be determined by the input voltage minus
the voltage drop across the P-channel MOSFET and the
inductor.
Undervoltage Lockout
To prevent operation of the external MOSFETs below safe
input voltage levels, an undervoltage lockout is incorporated
in the LTC3736-1. When the input supply voltage (V_IN)
drops below 2.3V, the external P- and N-channel MOSFETs
and all internal circuitry are turned off except for the und-
ervoltage block, which draws only a few microamperes.
Peak Current Sense Voltage Selection and Slope
Compensation (IPRG1 and IPRG2 Pins)
When a controller is operating below 20% duty cycle, the
peak current sense voltage (between the SENSE⁺ and SW
pins) allowed across the external P-channel MOSFET is
determined by:
( ) _{∆VSENSE(MAX)}
=
A
V_ITH – 0.7V
10
where A is a constant determined by the state of the IPRG
pins. Floating the IPRG pin selects A = 1; tying IPRG to V_IN
selects A = 5/3; tying IPRG to SGND selects A = 2/3. The
maximum value of V_ITH is typically about 1.98V, so the
12
maximum sense voltage allowed across the external
P-channel MOSFET is 125mV, 85mV or 204mV for the
three respective states of the IPRG pin. The peak sense
voltages for the two controllers can be independently
selected by the IPRG1 and IPRG2 pins.
However, once the controller’s duty cycle exceeds 20%,
slope compensation begins and effectively reduces the
peak sense voltage by a scale factor given by the curve in
Figure 2.
110
100
90
80
70
60
50
40
30
20
10
0
0 10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
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Figure 2. Maximum Peak Current vs Duty Cycle
The peak inductor current is determined by the peak sense
voltage and the on-resistance of the external P-channel
MOSFET:
I_PK
=
∆V_SENSE(MAX)
R_DS(ON)
Power Good (PGOOD) Pin
A window comparator monitors both feedback voltages
and the open-drain PGOOD output pin is pulled low when
either or both feedback voltages are not within ±10% of
the 0.6V reference voltage. PGOOD is low when the
LTC3736-1 is shut down or in undervoltage lockout.
2-Phase Operation
Why the need for 2-phase operation? Until recently, con-
stant frequency dual switching regulators operated both
controllers in phase (i.e., single phase operation). This
means that both topside MOSFETs (P-channel) are turned
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