LTC3736-1 Datasheet, PDF (20/28 Pages) Linear Technology – Dual 2-Phase, No RSENSE Synchronous Controller with Spread Spectrum

LTC3736-1
APPLICATIO S I FOR ATIO
change as the supply is reduced down to 2.4V. Also shown
is the effect on V_REF.
Minimum On-Time Considerations
Minimum on-time, t_ON(MIN), is the smallest amount of time
in which the LTC3736-1 is capable of turning the top
P-channel MOSFET on and then off. It is determined by
internal timing delays and the gate charge required to turn
on the top MOSFET. Low duty cycle and high frequency
applications may approach the minimum on-time limit
and care should be taken to ensure that:
t_ON(MIN)
<
V_OUT
f_OSC • V_IN
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3736-1 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase. The
minimum on-time for the LTC3736-1 is typically about
250ns. However, as the peak sense voltage (I_L(PEAK) •
R_DS(ON)) decreases, the minimum on-time gradually in-
creases up to about 300ns.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of the
losses in LTC3736-1 circuits: 1) LTC3736-1 DC bias
current, 2) MOSFET gate charge current, 3) I²R losses,
and 4) transition losses.
1) The V_IN (pin) current is the DC supply current, given in
the electrical characteristics, excluding MOSFET driver
currents. V_IN current results in a small loss that in-
creases with V_IN.
2) MOSFET gate charge current results from switching the
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from SENSE⁺ to ground.
The resulting dQ/dt is a current out of SENSE⁺, which is
typically much larger than the DC supply current. In
continuous mode, I_GATECHG = f • Q_P.
3) I²R losses are calculated from the DC resistances of the
MOSFETs and inductor. In continuous mode, the aver-
age output current flows through L but is “chopped”
between the top P-channel MOSFET and the bottom
N-channel MOSFET. The MOSFET R_DS(ON)s multiplied
by duty cycle can be summed with the resistance of L
to obtain I²R losses.
4) Transition losses apply to the top external P-channel
MOSFET and increase with higher operating frequen-
cies and input voltages. Transition losses can be esti-
mated from:
Transition Loss = 2 (V_IN)²I_O(MAX)C_RSS(f)
Other losses, including C_IN and C_OUT ESR dissipative
losses and inductor core losses, generally account for less
than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V_OUT immediately shifts by an amount
equal to (∆I_LOAD)(ESR), where ESR is the effective series
resistance of _COUT. ∆I_LOAD also begins to charge or dis-
charge C_OUT, which generates a feedback error signal. The
regulator loop then returns V_OUT to its steady-state value.
During this recovery time, V_OUT can be monitored for over-
shoot or ringing. OPTI-LOOP compensation allows the
transient response to be optimized over a wide range of
output capacitance and ESR values.
The I_TH series R_C-C_C filter (see Functional Diagram) sets
the dominant pole-zero loop compensation. The I_TH exter-
nal components shown in the Typical Application on the
front page of this data sheet will provide an adequate
starting point for most applications. The values can be
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