LTC3736-1 Datasheet, PDF (21/28 Pages) Linear Technology – Dual 2-Phase, No RSENSE Synchronous Controller with Spread Spectrum

LTC3736-1
APPLICATIO S I FOR ATIO
modified slightly (from 0.2 to 5 times their suggested
values) to optimize transient response once the final PC
layout is done and the particular output capacitor type and
value have been determined. The output capacitors need
to be decided upon because the various types and values
determine the loop feedback factor gain and phase. An
output current pulse of 20% to 100% of full load current
having a rise time of 1µs to 10µs will produce output
voltage and I_TH pin waveforms that will give a sense of the
overall loop stability. The gain of the loop will be increased
by increasing R_C, and the bandwidth of the loop will be
increased by decreasing C_C. The output voltage settling
behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C_LOAD).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3736-1. These items are illustrated in the layout dia-
gram of Figure 11. Figure 12 depicts the current wave-
forms present in the various branches of the 2-phase dual
regulator.
1) The power loop (input capacitor, MOSFETs, inductor,
output capacitor) of each channel should be as small as
possible and isolated as much as possible from the power
loop of the other channel. Ideally, the drains of the P- and
N-channel FETs should be connected close to one another
with an input capacitor placed across the FET sources
(from the P-channel source to the N-channel source) right
LTC3736EGN-1
1
SW1
SENSE1^{+ 24}
2
IPRG1
23
PGND
3
V_FB1
4
I_TH1
5
IPRG2
22
BG1
21
SSDIS
20
TG1
6
FREQ
19
PGND
7
SGND
18
TG2
8
V_IN
9
TRACK
17
RUN/SS
16
BG2
10
V_FB2
11
I_TH2
12
PGOOD
15
PGND
SENSE2^{+ 14}
13
SW2
C_OUT1
V_OUT1
L1
MN1 MP1
C_VIN1
C_VIN
C_VIN2
MN2
V_IN
MP2
L2
C_OUT2
BOLD LINES INDICATE HIGH CURRENT PATHS
V_OUT2
37361 F11
Figure 11. LTC3736-1 Layout Diagram
37361f
21