LTC3709_15 Datasheet, PDF (20/24 Pages) Linear Technology – Fast 2-Phase, No RSENSE Synchronous DC/DC Controller with Tracking/Sequencing

LTC3709
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
When laying out a PC board follow one of the two sug-
gested approaches. The simple PC board layout requires
a dedicated ground plane layer. Also, for higher currents,
it is recommended to use a multilayer board to help with
heat sinking power components.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
• Place C_IN, C_OUT, MOSFETs, D1, D2 and inductors all in
one compact area. It may help to have some compo-
nents on the bottom side of the board.
• Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3709.
Use several larger vias for power components.
• Use a compact plane for switch node (SW) to keep EMI
down.
• Use planes for V_IN and V_OUT to maintain good voltage
filtering and to keep power losses low.
• Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power component. You can connect the copper areas to
any DC net (V_IN, V_OUT, GND or to any other DC rail in
your system).
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera-
tion of the controller. These items are also illustrated in
Figure 9.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point, which is then tied to a “clean” point in the
power ground such as the “–” node of C_IN.
• Minimize impedance between input ground and output
ground.
• Connect PGND1 to the source of M2 or R_S1 (QFN)
directly. This also applies to channel 2.
• Place M2 as close to the controller as possible, keeping
the PGND1, BG1 and SW1 traces short. The same for
the other channel. SW2 trace should connect to the
drain of M2 directly.
• Connect the input capacitor(s) C_IN close to the power
MOSFETs: (+) node to drain of M1, (–) node to source
of M2. This capacitor carries the MOSFET AC current.
• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Connect the DRV_CC decoupling capacitor C_VCC closely
to the DRV_CC and PGND pins.
• Connect the top driver boost capacitor C_B closely to the
BOOST and SW pins.
• Connect the V_IN pin decoupling capacitor C_F closely to
the V_CC and PGND pins.
• Are the SENSE^– and SENSE⁺ leads routed together with
minimum PC trace spacing? The filter capacitor be-
tween SENSE^– and SENSE⁺ (C_SENSE) should be as close
as possible to the IC. Ensure accurate current sensing
with Kelvin connections at the sense resistor as shown
in Figure 8.
20
D
G
D
S
D
S
D
S
SENSE ⁺ SENSE ^–
MOSFET
(8a) Sensing the Bottom MOSFET
SENSE ⁺ SENSE ^–
(8b) Sensing a Resistor
R_SENSE
3709 F08
Figure 8. Kelvin Sensing
3709fb