LTC3709_15 Datasheet, PDF (13/24 Pages) Linear Technology – Fast 2-Phase, No RSENSE Synchronous DC/DC Controller with Tracking/Sequencing

LTC3709
APPLICATIO S I FOR ATIO
Both top and bottom MOSFETs have I²R losses and the top
MOSFET includes an additional term for transition losses,
which are the largest at maximum input voltages. The
bottom MOSFET losses are the greatest when the bottom
duty cycle is near 100%, during a short circuit or at high
input voltage. A much smaller and much lower input
capacitance MOSFET should be used for the top MOSFET
in applications that have an output voltage that is less than
1/3 of the input voltage. In applications where V_IN >> V_OUT,
the top MOSFETs’ “on” resistance is normally less impor-
tant for overall efficiency than its input capacitance at
operating frequencies above 300kHz. MOSFET manufac-
turers have designed special purpose devices that provide
reasonably low “on” resistance with significantly reduced
input capacitance for the main switch application in switch-
ing regulators.
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance to main-
tain low output ripple voltage.
The operating frequency of LTC3709 applications is deter-
mined implicitly by the one-shot timer that controls the on
time, t_ON, of the top MOSFET switch. The on-time is set by
the current into the I_ON pin according to:
( ) ^tON
=
0.7
I_ION
30pF
Tying a resistor from V_IN to the I_ON pin yields an on-time
inversely proportional to V_IN. For a down converter, this
results in approximately constant frequency operation as
the input supply varies:
f
=
0.7
•
V_OUT
R_ON (30pF)
(Per
Phase)
PLL and Frequency Synchronization
In the LTC3709, there are two on-chip phase-lock loops
(PLLs). One of the PLLs is used to achieve frequency
locking and phase separation between the two channels
while the second PLL is for locking onto an external clock.
Since the LTC3709 is a constant on-time architecture, the
error signal generated by the phase detector of the PLL is
used to vary the on-time to achieve frequency locking and
180° phase separation.
The synchronization is set up in a “daisy chain” manner
whereby channel 2’s on-time will be varied with respect to
channel 1. If an external clock is present, then channel 1’s
on-time will be varied and channel 2 will follow suit. Both
PLLs are set up with the same capture range and the fre-
quency range that the LTC3709 can be externally synchro-
nized to is between 2 • f_C and 0.5 • f_C, where f_C is the initial
frequency setting of the two channels. It is advisable to set
initial frequency as close to external frequency as possible.
A limitation of both PLLs is when the on-time is close to the
minimum (100ns). In this situation, the PLL will not be
able to synchronize up in frequency.
To ensure proper operation of the internal phase-lock loop
when no external clock is applied to the FCB pin, the
INTLPF pin may need to be pulled down while the output
voltage is ramping up. One way to do this is to connect the
anode of a silicon diode to the INTLPF pin and its cathode
to the PGOOD pin and connect a pull-up resistor between
the PGOOD pin and V_CC. Refer to Figure 9 for an example.
Inductor Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple current:
∆I_L
=
⎛
⎝⎜
V_OUT
f •L
⎞⎛
⎠⎟ ⎝⎜^1–
V_OUT
V_IN
⎞
⎠⎟
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
3709fb
13