LTC3709_15 Datasheet, PDF (11/24 Pages) Linear Technology – Fast 2-Phase, No RSENSE Synchronous DC/DC Controller with Tracking/Sequencing

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OPERATIO (Refer to Functional Diagram)
Differential Amplifier
This amplifier provides true differential output voltage
sensing. Sensing both V_OUT+ and V_OUT– benefits regula-
tion in high current applications and/or applications hav-
ing electrical interconnection losses. This sensing also
isolates the physical power ground from the physical
signal ground, preventing the possibility of troublesome
“ground loops” on the PC layout and preventing voltage
errors caused by board-to-board interconnects.
Dual Phase Operation
An internal phase-lock loop (PLL1) ensures that channel
2 operates exactly at the same frequency as channel 1 and
is also phase shifted by 180°, enabling the LTC3709 to
operate optimally as a dual phase controller. The loop filter
connected to the INTLPF pin provides stability to the PLL.
For external clock synchronization, a second PLL (PLL2)
is incorporated into the LTC3709. PLL2 will adjust the on-
time of channel 1 until its frequency is the same as the
external clock. When locked, the PLL2 aligns the turn on
LTC3709
of the top MOSFET of channel 1 to the rising edge of the
external clock. Compensation for PLL2 is through the
EXTLPF pin.
The loop filter components tied to the INTLPF and EXTLPF
pins are used to compensate the internal PPL and external
PLL respectively. The typical value ranges are:
INTLPF: R_IPLL = 2kΩ to 10kΩ, C_IPLL = 10nF to 100nF
EXTLP: R_EPLL ≤ 1kΩ, C_EPLL= 10nF to 100nF
For noise suppression, a capacitor with a value of 1nF or
less should be placed from INTLPF to ground and EXTLPF
to ground.
Second Channel Shutdown During Light Loads
When FCB is tied to V_CC, discontinuous mode is selected.
In this mode, no reverse current is allowed. The second
channel is off when I_TH is less than 0.8V for better
efficiency. When FCB is tied to ground, forced continuous
mode is selected, both channels are on and reversed
current is allowed.
APPLICATIO S I FOR ATIO
The basic LTC3709 application circuit is shown on the
first page of this data sheet. External component selec-
tion is primarily determined by the maximum load cur-
rent and begins with the selection of the power MOSFET
switches and/or sense resistor. The inductor current is
determined by the R_DS(ON) of the synchronous MOSFET
while the user has the option to use a sense resistor for
a more accurate current limiting. The desired amount of
ripple current and operating frequency largely deter-
mines the inductor value. Finally, C_IN is selected for its
ability to handle the large RMS current into the converter
and C_OUT is chosen with low enough ESR to meet the
output voltage ripple specification.
Maximum Sense Voltage and V_RNG Pin
Inductor current is determined by measuring the voltage
across the R_DS(ON) of the synchronous MOSFET or through
a sense resistance that appears between the SENSE^– and
the SENSE⁺ pins. The maximum sense voltage is set by the
voltage applied to the V_RNG pin and is equal to approxi-
mately V_RNG/7.5. The current mode control loop will not
allow the inductor current valleys to exceed V_RNG/(7.5 •
R_SENSE). In practice, one should allow some margin for
variations in the LTC3709 and external component values.
A good guide for selecting the sense resistance for each
channel is:
R_SENSE
=
2 • V_RNG
10 • I_OUT(MAX)
The voltage of the V_RNG pin can be set using an external
resistive divider from V_CC between 0.5V and 2V resulting
in nominal sense voltages of 50mV to 200mV. Addition-
ally, the V_RNG pin can be tied to ground or V_CC, in which
case the nominal sense voltage defaults to 70mV or
140mV, respectively. The maximum allowed sense volt-
age is about 1.3 times this nominal value.
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