LTC3709_15 Datasheet, PDF (19/24 Pages) Linear Technology – Fast 2-Phase, No RSENSE Synchronous DC/DC Controller with Tracking/Sequencing

LTC3709
APPLICATIO S I FOR ATIO
equal to ∆I_LOAD (ESR), where ESR is the effective series
resistance of C_OUT. ∆I_LOAD also begins to charge or
discharge C_OUT generating a feedback error signal used by
the regulator to return V_OUT to its steady-state value.
During this recovery time, V_OUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lems. The I_TH pin external components shown in Figure 9
will provide adequate compensation for most applica-
tions. For a detailed explanation of switching control loop
theory see Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: V_IN = 7V to 28V (15V nominal), V_OUT =
2.5V, I_OUT(MAX) = 20A, f = 250kHz. First, calculate the
timing resistor:
( )( )( ) ^{RON =}
0.7V
2.5V
250kHz
30pF
= 476k
and choose the inductor for about 40% ripple current at
the maximum V_IN. Maximum output current for each
channel is 10A:
( )( )( ) ^{L =}
2.5V
250kHz 0.4
10A
⎛
⎝⎜^1−
2.5V ^⎞
28V ⎠⎟
=
2.3µH
Selecting a standard value of 1.8µH results in a maximum
ripple current of:
( )( ) ^{∆IL =}
2.5V
250kHz 1.8µH
⎛
⎝⎜
1–
2.5V
28V
⎞
⎠⎟
= 5.1A
Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (R_DS(ON) = 0.0083Ω (NOM) 0.010Ω (MAX),
q_JA = 40°C/W) yields a nominal sense voltage of:
V_SNS(NOM) = (10A)(1.3)(0.0083Ω) = 108mV
Tying V_RNG to 1.1V will set the current sense voltage range
for a nominal value of 110mV with current limit occurring
at 146mV. To check if the current limit is acceptable,
assume a junction temperature of about 80°C above a
70°C ambient with ρ_150°C = 1.5:
( )( ) ^{( ) ⎛}
I_LIMIT ≥ _{⎝⎜⎜}
146mV
1.5 0.010Ω
+
1
2
5.1A
⎞
⎠⎟⎟
• 2 = 24A
and double check the assumed T_J in the MOSFET:
( )( ) ^PBOT
=
28 V – 2.5V ^⎛ 24A ^{⎞ 2}
28V ⎝⎜ 2 ⎠⎟
1.5
0.010Ω
= 1.97W
T_J = 70°C + (1.97W)(40°C/W) = 149°C
Because the top MOSFET is on for such a short time, an
Si4884 R_DS(ON)(MAX) = 0.0165Ω, C_RSS = 100pF, θ_JA =
40°C/W will be sufficient. Checking its power dissipation
at current limit with ρ_100°C = 1.4:
( )( ) ^PTOP
=
2.5V ^⎛ 24A^{⎞ 2}
28V ⎝⎜ 2 ⎠⎟
1.4
0.0165Ω
+
(^1.7)(^28V)²(^12A)(^100pF)(^250kHz)
= 0.30W + 0.40W = 0.7W
T_J = 70°C + (0.7W)(40°C/W) = 98°C
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
C_IN is chosen for an RMS current rating of about 10A
at 85°C. The output capacitors are chosen for a low ESR
of 0.013Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
∆V_OUT(RIPPLE) = ∆I_L(MAX) (ESR)
= (5.1A) (0.013Ω) = 66mV
However, a 0A to 10A load step will cause an output
change of up to:
∆V_OUT(STEP) = ∆I_LOAD (ESR) = (10A) (0.013Ω) = 130mV
An optional 22µF ceramic output capacitor is included to
minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 9.
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