LTC4417_15 Datasheet, PDF (18/32 Pages) Linear Technology – Prioritized PowerPat Controller

LTC4417
Applications Information
Absolute Maximum Ratings. If the BV_DSS of the external
P-channel MOSFET is momentarily exceeded, ensure the
avalanche energy absorbed by the MOSFETs do not exceed
the single pulse avalanche energy specification (EAS).
Voltage spikes can be dampened further with a snubber.
Input Supply and V_OUT Shorts
Input shorts can cause high current slew rates. Coupled
with series parasitic inductances in the input and output
paths, potentially destructive transients may appear at the
input and output pins. If the short occurs on an input that
is not powering V_OUT, the impact to the system is benign.
Back-to-back P-channel MOSFETs with their common gates
connected to their common sources naturally prevent any
current flow regardless of the applied voltages on either
side of the drain connections, as long as the BV_DSS is not
exceeded.
If the short occurs on an input that is powering V_OUT, the
issue is compounded by high conduction current and low
impedance connection to the output via the back-to-back
P-channel MOSFETs. Once the LTC4417 blocks the high
input short current, V1, V2 and V3 may experience large
negative voltage spikes while the output may experience
large positive voltage spikes.
To prevent damage to the LTC4417 and associated de-
vices in the event of an input or output short, it may be
necessary to protect the input pins and output pins as
shown in Figure 9. Protect the input pins, V1, V2 and V3,
with either unidirectional or bidirectional TVS and V_OUT
with a unidirectional TVS. An input and output capacitor
between 0.1µF and 10µF with intentional or parasitic series
resistance will aid in dampening voltage spikes; see Linear
Technology’s Application Note 88 for general consideration.
Due to the low impedance connection from V1, V2 and V3
to V_OUT, shorts to the output will result in an input supply
UV fault. If the UV threshold is high enough and the short
resistive enough, the LTC4417 will disconnect the input.
The fast change in current may force the output below
GND, while the input will increase in voltage.
If UV thresholds are set close to the minimum operating
voltage of the LTC4417, it may not disconnect the input
from the output before the output is dragged below the
operating voltage of the LTC4417. The event would cause
the LTC4417’s internal V_LDO supply voltage to collapse. A
100Ω and 10nF R-C filter on V_OUT will allow the LTC4417
to ride through such shorts to the input and output, as
shown in Figure 10. Because V_OUT is also a sense pin
for the REV comparator, care should be taken to ensure
the voltage drop across the resistor is low enough to not
affect the reverse comparator’s threshold. If the 1µs R-C
time constant does not address the issue, increase the
capacitance to lengthen the time constant.
IRF7324
M3
M4
IRF7324
M5
M6
VS2 G2
VS3 G3
R_F
V_OUT 100Ω _OUTPUT
LTC4417
V_OUT
C_F
10nF
+
C_L
I_L
4417 F10
Figure 10. R-C Filter to Ride Through Input Shorts
The initial lag due to the R-C filter on the LTC4417’s V_OUT
sense and supply pin will cause additional delay in sensing
when a reverse condition has cleared, resulting in addi-
tional droop when transitioning from a higher voltage to
a lower voltage. If the reverse voltage duration is longer
than the R-C delay, the voltage differential between the
output and the filtered V_OUT, ∆V, can be calculated with
Equation (18). I_L is the output load current during the
reverse voltage condition and I_VOUT is current into V_OUT,
specified in the electrical table.
ΔV
=
⎛
⎜
⎝
I_L
C_L
• C_F
⎞
–
I_VOUT
⎟
⎠
•
R_F
(18)
I_CC Path Selection
Two separate internal power rails ensure the LTC4417 is
functional when one or more input supplies are present
and above 2.4V as well as limit current draw from lower
4417f
18