LTC4417_15 Datasheet, PDF (10/32 Pages) Linear Technology – Prioritized PowerPat Controller

LTC4417
Operation
The Functional Block Diagram displays the main functional
blocks of this device. The LTC4417 connects one of three
power supplies to a common output, V_OUT, based on user
defined priority. Connection is made by enhancing external
back-to-back P-channel MOSFETs. Unlike a diode-OR,
which always passes the highest supply voltage to the
output, the LTC4417 lets one use a lower voltage supply
for primary power and a higher voltage supply as second-
ary or backup power.
During normal operation the LTC4417 continuously moni-
tors V1, V2 and V3 through its respective OV1, OV2 and OV3
and UV1, UV2 and UV3 pins using precision overvoltage
and undervoltage comparators. The highest priority input
supply whose voltage is within its respective OV/UV window
for at least 256ms is considered valid and is connected to
V_OUT through external back-to-back P-channel MOSFETs.
VALID1, VALID2 and VALID3 pull low to indicate when the
V1, V2 and V3 input supplies are valid.
Hysteresis on the OV and UV threshold is adjustable.
Connecting a resistor, R_HYS, between HYS and ground
forces 63mV/R_HYS current to flow out of OV1, OV2 and
OV3 and into UV1, UV2 and UV3 to create hysteresis when
outside their respective OV/UV windows. Connecting HYS
to ground sets the OV and UV comparator hysteresis to
30mV. See the Application Information for more details.
During channel transitions, monitoring circuitry prevents
cross conduction between input channels and reverse con-
duction from V_OUT using a break-before-make architecture.
The VGS comparator monitors the disconnecting channel’s
gate pin voltage (G1, G2 or G3). When the gate voltage is
350mV from its common source connection (VS1, VS2 or
VS3), the VGS comparator latches the output to indicate
the channel is off and allows the next valid priority input
supply to connect to V_OUT, preventing cross conduction
between channels. The latch is reset when the channel is
turned on.
To prevent reverse conduction from V_OUT to V1, V2 and V3
during channel switchover, the REV comparator monitors
the connecting input supply (V1, V2 or V3) and output
voltage (V_OUT). The REV comparator delays the connection
until the output voltage droops lower than the input voltage
by the reverse current blocking threshold of 120mV. The
output of the REV comparator is latched, resetting when
its respective channel is turned off.
The LTC4417 gate driver pulls down on G1, G2 and
G3 with a strong P-channel source follower and a 2µA
current source. When the clamp voltage is reached, the
P-channel source follower is back biased, leaving the
2µA current source to hold G1, G2 and G3 at the clamp
voltage. To minimize inrush current at start-up, the gate
driver soft-starts the first input supply to connect V_OUT,
at a rate of around 5V/ms terminating when any channel
disconnects or 32ms has elapsed. Once slew rate control
has terminated, the gate driver quickly turns on and off
external back-to-back P-channel MOSFETs as needed. A
SHDN low to high transition or V_OUT drooping below 0.7V
reactivates soft-start.
When EN is driven above 1V the highest valid priority
input supply is connected to V_OUT. The high voltage EN
comparator disconnects all channels when EN is driven
below 1V. The LTC4417 continues to monitor the OV and
UV pins and reflects the current input supply status with
VALID1, VALID2 and VALID3. When four or more sup-
plies need to be prioritized, connect the higher priority
LTC4417’s CAS to the lower priority LTC4417’s EN. If
V_OUT is allowed to fall below 0.7V, the next connecting
input supply is soft-started.
The high voltage SHDN comparator forces the LTC4417 into
a low current state when SHDN is forced below 0.8V. While
in the low current state, all channels are disconnected, OV
and UV comparators are disabled, and all 256ms timers
are reset. When SHDN transitions from low to high, the
first validated input to connect to V_OUT is soft-started.
Two separate internal power rails ensure the LTC4417 is
functional when one or more input supply is present and
above 2.3V. V_BESTGEN generates a VB_LDO rail from the
highest V1, V2 and V3 and V_OUT voltage. VB_LDO powers
the UVLO, bandgap, and V_OUT comparator. The internal
V_LDO powers all other circuits from V_OUT provided V_OUT is
greater than 2.4V. If V_OUT is less than 2.3V, V_LDO powers
all other circuits from the highest priority supply available.
If all sources are invalid or the LTC4417 is shut down,
V_LDO connects to VB_LDO.
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