LTC4417_15 Datasheet, PDF (17/32 Pages) Linear Technology – Prioritized PowerPat Controller

LTC4417
Applications Information
P-channel’s gate to source voltage when driving the load
and inrush current, C_S is the slew rate capacitor and C_L
is the V_OUT hold up capacitance. The output load current
I_L is neglected for simplicity. Choose C_S to be at least ten
times the external P-channel MOSFET’s C_RSS(MAX), and
C_VS to be ten times C_S.
( ) _{RS ≥}
ΔV_G(SINK) – V_GS • C_L • R_SRC
C_S • V1_DROOP
(16)
Use Equation (17) to verify the inrush current limit is lower
than the absolute maximum pulsed drain current, I_DM.
I_INRUSH
=
V1_DROOP
R_SRC
(17)
If the external P-channel MOSFET’s reverse transfer
capacitance, C_RSS, is used instead of C_S, replace C_S with
C_RSS in Equation (16), where C_RSS is taken at the minimum
V_DS voltage, and calculate for R_S. Depending on the size
of C_RSS, R_S may be large. Care should be used to ensure
gate leakages do not inadvertently turn off the channel over
temperature. This is particularly true of built in Zener gate-
source protected devices. Careful bench characterization
is strongly recommended, as C_RSS is non-linear.
The preceding analysis assumes a small input inductance
between the input supply voltage and the drain of the ex-
ternal P-channel MOSFET. If the input inductance is large,
choose C_V1 to be much greater than C_L and replace R_SRC
with the ESR of C_V1.
When slew rate limiting the output, ensure power dis-
sipation does not exceed the manufacturer’s SOA for the
chosen external P-channel MOSFET. Refer to the Selecting
External P-channel MOSFETs section.
Transient Supply Protection
The LTC4417’s abrupt switching due to OV or UV faults
can create large transient overvoltage events with inductive
input supplies, such as supplies connected by a long cable.
At times the transient overvoltage condition can exceed
twice the nominal voltage. Such events can damage external
devices and the LTC4417. It is imperative that external
back-to-back P-channel MOSFET devices do not exceed
their single pulse avalanche energy specification (EAS) in
unclamped inductive applications and input voltages to the
LTC4417 never exceed the Absolute Maximum Ratings.
To minimize inductive voltage spikes, use wider and/or
heavier trace plating. Adding a snubber circuit will dampen
input voltage spikes as discussed in Linear Application
Note 88, and a transient surge suppressor at the input will
clamp the voltage. Transient voltage suppressors (TVS)
should be placed on any input supply pin, V1, V2 and V3,
where input shorts, or reverse voltage connection can be
made. If short-circuit of input sources powering V_OUT are
possible, transient voltage suppressors should also be
placed on V_OUT, as shown in Figure 9.
When selecting transient voltage suppressors, ensure the
reverse standoff voltage (V_R) is equal to or greater than
the application operating voltage, the peak pulse current
(I_PP) is higher than the peak transient voltage divided by
the source impedance, the maximum clamping voltage
(V_CLAMP) at the rated I_PP is less than the absolute maxi-
mum ratings of the LTC4417 and BV_DSS of all the external
back-to-back P-channel MOSFETs.
In applications below 20V, transient voltage suppressors
may not be required if the voltage spikes are lower than the
BV_DSS of the external P-channel MOSFETs and the LTC4417
24V WALL
ADAPTER
INPUT
PARASITIC
INDUCTANCE
R_SN ^OR
C_SN
SNUBBER
D1
SMBJ26CA
FDD4685
M1
C_V1
0.1µF
FDD4685
M2
VS1 G1
LTC4417
V_OUT
4417 F09
Figure 9. Transient Voltage Suppression
C_OUT ^OR
10µF
OUTPUT
PARASITIC
INDUCTANCE
+
D2
SMBJ26A
V_OUT
C_L
330µF
4417f
17