LTC4417_15 Datasheet, PDF (15/32 Pages) Linear Technology – Prioritized PowerPat Controller

LTC4417
Applications Information
Table 1. List of Suggested P-Channel MOSFETs
V1, V2, V3
≤5V
MOSFET
Si4465ADY
V_TH(MAX) V_GS(MAX) V_DS(MAX)
–1V ±8V –8V
MAX RATED
R_DS(ON) AT 25°C
9mΩ at –4.5V
11mΩ at –2.5V
≤10V Si4931DY* –1V ±8V –12V 18mΩ at –4.5V
22mΩ at –2.5V
≤18V FDS8433A –1V ±8V –20V 47mΩ at –4.5V
70mΩ at –2.5V
≤18V IRF7324* –1V ±12V –20V 18mΩ at –4.5V
26mΩ at –2.5V
≤28V Si7135DP –3V ±20V –30V 6.2mΩ at –4.5V
≤28V FDS6675BNZ –3V ±20V –30V 22mΩ at –4.5V
≤28V AO4803A* –2.5V ±20V –30V 46mΩ at –4.5V
≤36V SUD50P04 –2.5V ±20V –40V 30mΩ at –4.5V
≤36V FDD4685 –3V ±20V –40V 35mΩ at –4.5V
≤36V FDS4685 –3V ±20V –40V 35mΩ at –4.5V
≤36V Si4909DY* –2.5V ±20V –40V 34mΩ at –4.5V
≤36V Si7489DP –3V ±20V –100V 47mΩ at –4.5V
*Denotes Dual P-Channel
V2 = 18V
V_OUT
V1 VALIDATES
V1 = 12V
256ms
V2 DISCONNECTS
dV_OUT
dt
=
I_L
C_L
V_OUT
V1 = 12V
V_REV =
120mV
V1 CONNECTS AT
V_OUT = 11.88V
4417 F07
Figure 7. Reverse Current Blocking
The LTC4417 validates V1 and disconnects V2, allowing
V_OUT to decay from 18V to 11.88V at a slew rate determined
by the load current divided by the load capacitance. Once
V_OUT falls to 11.88V, the LTC4417 connects V1 to V_OUT.
Reverse Voltage Protection
The LTC4417 is designed to withstand reverse voltages
applied to V1, V2 and V3 with respect to V_OUT of up to
–84V. The large reverse voltage rating protects 36V input
supplies and downstream devices connected to V_OUT
against high reverse voltage connections of –42V (absolute
maximum) with margin.
Select back-to-back P-channel MOSFETS with BV_DSS(MAX)
ratings capable of handling any anticipated reverse voltages
between V_OUT and V1, V2 or V3. Ensure transient voltage
suppressors (TVS) connected to reverse connection pro-
tected inputs (V1, V2 and V3) are bidirectional and input
capacitors are rated for the negative voltage.
Reverse Current Blocking
When switching channels from higher voltages to lower
voltages, the REV comparator verifies the V_OUT voltage is
below the connecting channel’s voltage by 120mV before
the new channel is allowed to connect to V_OUT. This ensures
little to no reverse conduction occurs during switching.
An example is shown in Figure 7. V2 is initially connected
to V_OUT when a higher priority input supply, V1, is inserted.
Selecting V_OUT Capacitance
To ensure there is minimal droop at the output, select a
low ESR capacitor large enough to ride through the dead
time between channel switchover. A low ESR bulk capacitor
will reduce IR drops to the output voltage while the load
current is sourced from the capacitor. Use Equation (13)
to calculate the load capacitor value that will ride through
the OV/UV comparator delay, t_pVALID(OFF), plus the break-
before-make time, t_{G(SWITCHOVER)}.
( ) _CL
I_L(MAX) • t_{G(SWITCHOVER)} + t_pVALID(OFF)
V_{OUT _DROOP(MAX)}
(13)
where I_L(MAX) is the maximum load current drawn and
V_{OUT_DROOP(MAX)} is the maximum acceptable amount of
voltage droop at the output.
Equation (13) assumes no inrush current limiting circuitry
is required. If it is required, refer to Figure 8 and use the
following Equation (14) for C_L.
C_L ≥
(14)
( ) ^IL(MAX) ^{• t}G(SWITCHOVER) ^{+ t}pVALID(OFF) ^{+ 0.79 •R}S ^{• C}S
V_{OUT _DROOP(MAX)}
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