LTC3826-1 Datasheet, PDF (15/32 Pages) Linear Technology – 30μA IQ, Dual, 2-Phase Synchronous Step-Down Controller

LTC3826-1
APPLICATIONS INFORMATION
The MOSFET power dissipations at maximum output
current are given by:
( ) ( ) P_MAIN
=
V_OUT
V_IN
I_MAX
2
1+

R_DS(ON) +
(
V_IN
)²


I_MAX
2


(^R_DR
)(C_MILLER
)
•
( ) ^


V_INTVCC
1
–
V_THMIN
+
1
V_THMIN



f
( ) ( ) P_SYNC
=
V_IN
– V_OUT
V_IN
I_MAX
2
1+ δ R_DS(ON)
where δ is the temperature dependency of R_DS(ON) and
R_DR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. V_THMIN is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I²R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V_IN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for V_IN > 20V the transition losses rapidly
increase to the point that the use of a higher R_DS(ON) device
with lower C_MILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R_DS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diodes D3 and D4 shown in Figure 14
conduct during the dead-time between the conduction of
the two power MOSFETs. This prevents the body diode of
the bottom MOSFET from turning on, storing charge during
the dead-time and requiring a reverse recovery period that
could cost as much as 3% in efficiency at high V_IN. A 1A
to 3A Schottky is generally a good compromise for both
regions of operation due to the relatively small average
current. Larger diodes result in additional transition losses
due to their larger junction capacitance.
C_IN and C_OUT Selection
The selection of C_IN is simplified by the 2-phase architecture
and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It
can be shown that the worst-case capacitor RMS current
occurs when only one controller is operating. The controller
with the highest (V_OUT)(I_OUT) product needs to be used
in the formula below to determine the maximum RMS
capacitor current requirement. Increasing the output
current drawn from the other controller will actually
decrease the input RMS ripple current from its maximum
value. The out-of-phase technique typically reduces the
input capacitor’s RMS ripple current by a factor of 30%
to 70% when compared to a single phase power supply
solution.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (V_OUT)/(V_IN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
( )( ) ^C_IN
Required
I_RMS
≈
I_MAX
V_IN
⎡⎣
V_OUT
V_IN – V_OUT ⎤⎦^1/2
This formula has a maximum at V_IN = 2V_OUT, where I_RMS
= I_OUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3826-1, ceramic capacitors
can also be used for C_IN. Always consult the manufacturer
if there is any question.
The benefit of the LTC3826-1 2-phase operation can be
calculated by using the equation above for the higher
power controller and then calculating the loss that would
have resulted if both controller channels switched on at
the same time. The total RMS power lost is lower when
both controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s ESR.
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