ICE40HX1K-VQ100 Datasheet, PDF (9/12 Pages) Lattice Semiconductor – iCE40™ HX-Series Ultra Low-Power FPGA Family

iCE40 HX-Series Ultra-Low Power Family
Phase-Locked Loop (PLL) Block
Table 11 provides timing information for the Phase-Locked Loop (PLL) block shown in Figure 10.
Figure 10: Phase-Locked Loop (PLL)
PLL
LATCHINPUTVALUE
DYNAMICDELAY[3:0]
EXTFEEDBACK
BYPASS
RESET
LOCK
REFERENCECLK PLLOUT
Symbol From To
Frequency Range
F_REF
F_OUT
Duty Cycle
PLL_IJ
Tw_HI
Tw_LOW
PLL_OJ
Fine Delay
t_FDTAP
PLL_TAPS
PLL_FDAM
Jitter
PLL_IPJ
PLL_OPJ
Lock/Reset Time
t_LOCK
tw_RST
Notes:
Table 11: Phase-Locked Loop (PLL) Block Timing
Nominal VCC
1.2 V
Description
Min.
Typical
Max.
Units
Input clock frequency range
10
Output clock frequency range (cannot exceed
16
maximum frequency supported by global
buffers)
—
133
MHz
—
533
MHz
Input duty cycle
Input clock high time
Input clock low time
Output duty cycle
35
—
65
%
2.5
—
—
ns
2.5
—
—
ns
45
—
55
%
Fine delay adjustment, per tap
Fine delay adjustment settings
Maximum delay adjustment
165
ps
0
—
15
taps
2.5
ns
Input clock period jitter
PLLOUT output period jitter
—
—
+/- 300 ps
—
1% or +/- 1.1% ps
≤ 100
output
period or
≥ 110
PLL lock time after receive stable, monotonic
—
—
50
μs
REFERENCECLK input
Minimum reset pulse width
20
—
—
ns
1. Output jitter performance is affected by input jitter. A clean reference clock < 100ps jitter must be used to ensure
best jitter performance.
2. The output jitter specification refers to the intrinsic jitter of the PLL.
Lattice Semiconductor Corporation
www.latticesemi.com/
(1.32, 03-OCT-2012)
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