ICE40HX1K-VQ100 Datasheet, PDF (10/12 Pages) Lattice Semiconductor – iCE40™ HX-Series Ultra Low-Power FPGA Family

iCE40 HX-Series Ultra-Low Power Family
Internal Configuration Oscillator Frequency
Table 12 shows the operating frequency for the iCE40’s internal configuration oscillator.
Symbol
f_OSCD
f_OSCL
f_OSCH
Oscillator
Mode
Default
Low
Frequency
High
Frequency
Off
Table 12: Internal Oscillator Frequency at VCC = 1.2V
Frequency (MHz)
Min.
Max.
Description
7
10 Default oscillator frequency. Slow enough to safely operate
with any SPI serial PROM.
21
30 Supported by most SPI serial Flash PROMs
35
50 Supported by some high-speed SPI serial Flash PROMs
0
0
Oscillator turned off by default after configuration to save
power.
Configuration Timing
Table 13 shows the maximum time to configure an iCE40HX device, by oscillator mode. The calculations use the
slowest frequency for a given oscillator mode from Table 12 and the maximum configuration bitstream size from
Table 1, which includes full RAM4K block initialization. The configuration bitstream selects the desired oscillator
mode based on the performance of the configuration data source.
Symbol
t_CONFIGL
Table 13: Typical SPI Master or NVCM Configuration Timing by Oscillator Mode
Description
Device
Default
Low Freq. High Freq.
Time from when minimum
iCE40HX1K
53
25
11
Power-on Reset (POR)
threshold is reached until
iCE40HX4K
230
110
50
user application starts.
iCE40HX8K
230
110
50
Units
ms
ms
ms
Table 14 provides timing for the CRESET_B and CDONE pins.
Table 14: General Configuration Timing
Symbol
t_{CRESET_B}
t_{DONE_IO}
From
CREST_B
CDONE
High
To
CREST_B
PIO pins
active
Description
Minimum CRESET_B Low pulse width required to restart
configuration, from falling edge to rising edge
Number of configuration clock cycles after CDONE goes
High before the PIO pins are activated.
SPI Peripheral Mode (Clock = SPI_SCK, cycles measured
rising-edge to rising-edge)
All Grades
Min. Max.
200
—
—
49
Depends on
SPI_SCK frequency
Units
ns
Clock
cycles
Table 15 provides various timing specifications for the SPI peripheral mode interface.
Table 15: SPI Peripheral Mode Timing
Symbol From
To
Description
t_{CR_SCK}
CRESET_B _{SPI_SCK Minimum time from a rising edge on CRESET_B until}
the first SPI write operation, first SPI_SCK. During this
time, the iCE40HX FPGA is clearing its internal
configuration memory
t_SUSPISI
SPI_SI SPI_SCK Setup time on SPI_SI before the rising SPI_SCK clock
edge
t_HDSPISI
SPI_SCK SPI_SI Hold time on SPI_SI after the rising SPI_SCK clock edge
t_SPISCKH
t_SPISCKL
SPI_SCK SPI_SCK SPI_SCK clock High time
SPI_SCK SPI_SCK SPI_SCK clock Low time
t_SPISCKCYC SPI_SCK SPI_SCK SPI_SCK clock period*
F_{SPI_SCK}
SPI_SCK SPI_SCK Sustained SPI_SCK clock frequency*
* = Applies after sending the synchronization pattern.
All Grades
Min. Max.
300
—
12
—
12
—
20
—
20
—
40
1,000
1
25
Units
µs
ns
ns
ns
ns
ns
MHz
Lattice Semiconductor Corporation
www.latticesemi.com/
(1.32, 03-OCT-2012)
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