ICE40HX1K-VQ100 Datasheet, PDF (7/12 Pages) Lattice Semiconductor – iCE40™ HX-Series Ultra Low-Power FPGA Family

iCE40 HX-Series Ultra-Low Power Family
Programmable Input/Output (PIO) Block
Table 9 provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths
shown in Figure 7 and Figure 8. The timing shown is for the LVCMOS25 I/O standard in all I/O banks. The
iCEcube2 development software reports timing adjustments for other I/O standards.
Figure 7: Programmable I/O (PIO) Pad-to-Pad Timing Circuit
PAD _PIO
PIO ^PAD
Figure 8: Programmable I/O (PIO) Sequential Timing Circuit
PAD PIO
INFF
DQ
OUTFF
DQ
PIO ^PAD
GBIN GBUF
Table 9: Typical Programmable Input/Output (PIO) Timing (LVCMOS25)
Nominal VCC
1.2 V
Description
Typ.
Synchronous Output Paths
t_OCKO
OUTFF
PIO Delay from clock input on OUTFF output flip-flop to PIO output
3.1
clock _output pad.
input
t_GBCKIO
GBIN
OUTFF _{Global Buffer Input (GBIN) delay, though Global Buffer (GBUF)}
1.4
input
clock clock network to clock input on the PIO OUTFF output flip-flop.
input
Synchronous Input Paths
t_SUPDIN
PIO
GBIN Setup time on PIO input pin to INFF input flip-flop before active
0
input
input ^{clock edge on GBIN input, including interconnect delay.}
t_HDPDIN
GBIN
PIO Hold time on PIO input to INFF input flip-flop after active clock
1.6
input
input ^{edge on the GBIN input, including interconnect delay.}
Pad to Pad
t_PADIN
PIO
Inter- Asynchronous delay from PIO input pad to adjacent
1.8
input ^{connect interconnect.}
t_PADO
Inter-
PIO Asynchronous delay from adjacent interconnect to PIO output
3.4
connect _output pad including interconnect delay.
units
ns
ns
ns
ns
ns
ns
Lattice Semiconductor Corporation
www.latticesemi.com/
(1.32, 03-OCT-2012)
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