ICE40HX1K-VQ100 Datasheet, PDF (8/12 Pages) Lattice Semiconductor – iCE40™ HX-Series Ultra Low-Power FPGA Family

iCE40 HX-Series Ultra-Low Power Family
RAM4K Block
Table 10 provides timing information for the logic in a RAM4K block, which includes the paths shown in Figure 9.
Figure 9: RAM4K Timing Circuit
PAD
PIO _WDATA
RDATA
PIO ^PAD
GBIN GBUF
WCLK
RAM4K
RAM Block
(256x16)
RCLK
GBUF GBIN
Table 10: Typical RAM4K Block Timing
Nominal VCC
Description
Write Setup/Hold Time
t_SUWD
PIO
input
GBIN Minimum write data setup time on PIO inputs before active clock
input ^{edge on GBIN input, include interconnect delay.}
t_HDWD
GBIN
input
PIO Minimum write data hold time on PIO inputs after active clock edge
input ^{on GBIN input, including interconnect delay.}
Read Clock-Output-Time
t_CKORD
RCLK PIO Clock-to-output delay from RCLK input pin, through RAM4K RDATA
clock output ^{output flip-flop to PIO output pad, including interconnect delay.}
input
t_GBCKRM
GBIN
input
RCLK Global Buffer Input (GBIN) delay, though Global Buffer (GBUF)
clock ^{clock network to the RCLK clock input.}
input
Write and Read Clock Characteristics
t_RMWCKH
t_RMWCKL
t_RMWCYC
F_WMAX
WCLK
RCLK
WCLK
RCLK
Write clock High time
Write clock Low time
Write clock cycle time
Sustained write clock frequency
1.2 V
Typ.
0.44
0
4.1
1.4
0.30
0.35
0.71
256
ns
ns
ns
ns
ns
ns
ns
MHz
Lattice Semiconductor Corporation
www.latticesemi.com/
(1.32, 03-OCT-2012)
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