ICE40HX1K-VQ100 Datasheet, PDF (6/12 Pages) Lattice Semiconductor – iCE40™ HX-Series Ultra Low-Power FPGA Family

iCE40 HX-Series Ultra-Low Power Family
AC Timing Guidelines
The following examples provide some guidelines of device performance. The actual performance depends on the
specific application and how it is physically implemented in the iCE40 FPGA using the Lattice iCEcube2 software.
The following guidelines assume typical conditions (VCC = 1.0 V or 1.2 V as specified, temperature = 25 ˚C). Apply
derating factors using the iCEcube2 timing analyzer to adjust to other operating regimes.
Programmable Logic Block (PLB) Timing
Table 8 provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths
shown in Figure 5 and Figure 6.
Figure 5 PLB Sequential Timing Circuit
PAD
PIO
DFF
DQ
PIO ^PAD
LUT4
GBIN GBUF
LLooggiicc CCeellll
Figure 6 PLB Combinational Timing Circuit
PAD
PIO
PIO ^PAD
LUT4
Logic Cell
Table 8: Typical Programmable Logic Block (PLB) Timing
Nominal VCC
Description
Sequential Logic Paths
F_TOGGLE
GBIN
input
GBIN
input
Flip-flop toggle frequency. DFF flip-flop output fed back to LUT4 input with
4-input XOR, clocked on same clock edge
t_CKO
DFF
clock
PIO ^{Logic cell flip-flop (DFF) clock-to-output time, measured from the DFF CLK}
output ^{input to PIO output, including interconnect delay.}
input
t_GBCKLC
GBIN
input
DFF
clock
Global Buffer Input (GBIN) delay, though Global Buffer (GBUF) clock network
to clock input on the logic cell DFF flip-flop.
input
t_SULI
PIO
input
GBIN
input
Minimum setup time on PIO input, through LUT4, to DFF flip-flop D-input
before active clock edge on the GBIN input, including interconnect delay.
t_HDLI
GBIN
input
PIO
input
Minimum hold time on PIO input, through LUT4, to DFF flip-flop D-input
after active clock edge on the GBIN input, including interconnect delay.
Combinational Logic Paths
t_LUT4IN
PIO
input
LUT4
input
Asynchronous delay from PIO input pad to adjacent PLB interconnect.
t_ILO
LUT4 LUT4 ^{Logic cell LUT4 combinational logic propagation delay, regardless of logic}
input output ^{complexity from input to output.}
t_LUT4IN
LUT4 PIO Asynchronous delay from adjacent PLB interconnect to PIO output
output output ^pad.
1.2 V
Typ.
256
3.9
1.5
.67
0
1.8
0.34
3.7
units
MHz
ns
ns
ns
ns
ns
ns
ns
Lattice Semiconductor Corporation
www.latticesemi.com/
(1.32, 03-OCT-2012)
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