10321111 Datasheet, PDF (8/19 Pages) Lattice Semiconductor – High-Density Programmable Logic

Specifications ispLSI and pLSI 1032
ispLSI and pLSI 1032 Timing Model
I/O Cell
GRP
Ded. In
I/O Pin
(Input)
#55
#26
I/O Reg Bypass
#20
Input
D ^Register Q
RST
#21 - 25
Reset
GRP 4
#28
GRP
Loading
Delay
#27, 29,
30, 31, 32
Feedback
GLB
4 PT Bypass
#33
20 PT
XOR Delays
#34, 35, 36
#55
GLB Reg Bypass
#37
GLB Reg
Delay
D
Q
RST
#38, 39,
40, 41
ORP
I/O Cell
ORP Bypass
#46
ORP
Delay
#45
#47
I/O Pin
(Output)
#48, 49
Y1,2,3
Y0
Clock
Distribution
#51, 52,
53, 54
#50
Control _RE
PTs _OE
#42, 43, CK
44
Derivations of tsu, th and tco from the Product Term Clock¹
tsu = Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min))
= (#20 + #28 + #35) + (#38) - (#20 + #28 + #44)
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (2.0 + 2.0 + 3.5)
th
= Clock (max) + Reg h - Logic
= (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#20 + #28 + #44) + (#39) - (#20 + #28 + #35)
4.0 ns = (2.0 + 2.0 + 7.5) + (4.5) - (2.0 + 2.0 + 8.0)
tco = Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
= (#20 + #28 + #44) + (#40) + (#45 + #47)
19.0 ns = (2.0+ 2.0 +7.5) + (2.0) + (2.5 + 3.0)
Derivations of tsu, th and tco from the Clock GLB¹
tsu = Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min))
= (#20 + #28 + #35) + (#38) - (#50 + #40 + #52)
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (4.5 + 2.0 + 1.0)
th
= Clock (max) + Reg h - Logic
= (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#50 + #40 + #52) + (#39) - (#20 + #28 + #35)
4.0 ns = (4.5 + 2.0 + 5.0) + (4.5) - (2.0 + 2.0 + 8.0)
tco = Clock (max) + Reg co + Output
= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#50 + #40 + #52) + (#40) + (#45 + #47)
19.0 ns = (4.5 + 2.0 + 5.0) + (2.0) + (2.5 + 3.0)
1. Calculations are based upon timing specifications for the ispLSI and pLSI 1032-80.
8
1996 ISP Encyclopedia