10321111 Datasheet, PDF (5/19 Pages) Lattice Semiconductor – High-Density Programmable Logic

Specifications ispLSI and pLSI 1032
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER ^{TEST 5} #² DESCRIPTION¹
COND.
-90
-80
-60
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A 1 Data Propagation Delay, 4PT bypass, ORP bypass – 12 – 15 – 20 ns
tpd2
A 2 Data Propagation Delay, Worst Case Path
– 17 – 20 – 25 ns
fmax (Int.)
A 3 Clock Frequency with Internal Feedback³
90.9 – 80 – 60 – MHz
fmax (Ext.)
–
4
Clock
Frequency
with
External
Feedback _(tsu2
1
+
) _tco1
58.8 –
50
–
38
– MHz
fmax (Tog.) – 5 Clock Frequency, Max Toggle⁴
125 – 100 – 83 – MHz
tsu1
– 6 GLB Reg. Setup Time before Clock, 4PT bypass
6 – 7 – 9 – ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP bypass
– 8 – 10 – 13 ns
th1
– 8 GLB Reg. Hold Time after Clock, 4 PT bypass
0 – 0 – 0 – ns
tsu2
– 9 GLB Reg. Setup Time before Clock
9 – 10 – 13 – ns
tco2
– 10 GLB Reg. Clock to Output Delay
– 10 – 12 – 16 ns
th2
– 11 GLB Reg. Hold Time after Clock
0 – 0 – 0 – ns
tr1
A 12 Ext. Reset Pin to Output Delay
– 15 – 17 – 22.5 ns
trw1
– 13 Ext. Reset Pulse Duration
10 – 10 – 13 – ns
ten
B 14 Input to Output Enable
– 15 – 18 – 24 ns
tdis
C 15 Input to Output Disable
– 15 – 18 – 24 ns
twh
– 16 Ext. Sync. Clock Pulse Duration, High
4 – 5 – 6 – ns
twl
– 17 Ext. Sync. Clock Pulse Duration, Low
4 – 5 – 6 – ns
tsu5
– 18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) 2 – 2 – 2.5 – ns
th5
– 19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 6.5 – 6.5 – 8.5 – ns
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
Table 2-0030-32/90,80,60C
5
1996 ISP Encyclopedia