10321111 Datasheet, PDF (14/19 Pages) Lattice Semiconductor – High-Density Programmable Logic

Specifications ispLSI and pLSI 1032
Pin Description
Name
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
IN 4 - IN 7
ispEN*/NC
SDI*/IN 0
MODE*/IN 1
SDO*/IN 2
SCLK*/IN 3
RESET
Y0
Y1
Y2
Y3
NC
GND
VCC
CPGA Pin Numbers
Description
F1,
K1,
K3,
L4,
L7,
K8,
L11,
J11,
E9,
B11,
B9,
A8,
A5,
B4,
A1,
C1,
H1,
J2,
L2,
J5,
K7,
L9,
K10,
H10,
D11,
C10,
A10,
B6,
B5,
A3,
B2,
D2,
H2,
L1,
L3,
K5,
L6,
L10,
J10,
H11,
D10,
A11,
A9,
B7,
C5,
A2,
C2,
D1,
J1,
K2,
K4,
L5,
L8,
K9,
K11,
F10,
C11,
B10,
B8,
A7,
A4,
B3,
B1,
E3
E10, C7, A6, E2
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
Dedicated input pins to the device.
G3
G2
K6
J7
G10
G1
E1
E11
G9
G11
G3
C6, F3, F9, J6
F2, F11
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
Input/Output – This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input – This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
This pin should be left floating or tied to V
CC.
This pin should never be tied to GND.
Ground (GND)
V_CC
Table 2-0002-32/883
14
1996 ISP Encyclopedia