10321111 Datasheet, PDF(2/19 Page) Lattice Semiconductor

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10321111 Datasheet, PDF (2/19 Pages) Lattice Semiconductor – High-Density Programmable Logic

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Specifications ispLSI and pLSI 1032

Functional Block Diagram

Figure 1. ispLSI and pLSI 1032 Functional Block Diagram

RESET

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O I/O I/O I/O I/O I/O I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 7 6

Generic

Logic Blocks

(GLBs)

Input Bus

Output Routing Pool (ORP)

D7 D6 D5 D4 D3 D2 D1 D0

Global

Routing

Pool

(GRP)

IN 5

IN 4

I/O 47

I/O 46

I/O 45

I/O 44

I/O 43

I/O 42

I/O 41

I/O 40

I/O 39

I/O 38

I/O 37

I/O 36

I/O 35

I/O 34

I/O 33

I/O 32

*SDI/IN 0

*MODE/IN 1

B0 B1 B2 B3 B4 B5 B6 B7

Megablock

*ispEN/NC

Output Routing Pool (ORP)

Input Bus

*SDO/IN 2

*SCLK/IN 3

I/O I/O I/O I/O I/O I/O I/O I/O

16 17 18 19 20 21 22 23

*ISP Control Functions for ispLSI 1032 Only

I/O I/O I/O I/O

24 25 26 27

I/O I/O I/O I/O

28 29 30 31

Clock

Distribution

Network

CLK 0

CLK 1

CLK 2

IOCLK 0

IOCLK 1

YYYY

0123

0139(1)-32-isp

The devices also have 64 I/O cells, each of which is

directly connected to an I/O pin. Each I/O cell can be

individually programmed to be a combinatorial input,

registered input, latched input, output or bi-directional

I/O pin with 3-state control. Additionally, all outputs are

polarity selectable, active high or active low. The signal

levels are TTL compatible voltages and the output drivers

can source 4 mA or sink 8 mA.

Eight GLBs, 16 I/O cells, two dedicated inputs and one

ORP are connected together to make a Megablock (see

figure 1). The outputs of the eight GLBs are connected to

a set of 16 universal I/O cells by the ORP. The I/O cells

within the Megablock also share a common Output

Enable (OE) signal. The ispLSI and pLSI 1032 devices

contain four of these Megablocks.

The GRP has as its inputs the outputs from all of the GLBs

and all of the inputs from the bi-directional I/O cells. All of

these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI and pLSI 1032 devices are selected

using the Clock Distribution Network. Four dedicated

clock pins (Y0, Y1, Y2 and Y3) are brought into the

distribution network, and five clock outputs (CLK 0, CLK

1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route

clocks to the GLBs and I/O cells. The Clock Distribution

Network can also be driven from a special clock GLB (C0

on the ispLSI and pLSI 1032 devices). The logic of this

GLB allows the user to create an internal clock from a

combination of internal signals within the device.

1996 ISP Encyclopedia

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