10321111 Datasheet, PDF (7/19 Pages) Lattice Semiconductor – High-Density Programmable Logic

Specifications ispLSI and pLSI 1032
Internal Timing Parameters¹
PARAMETER #² DESCRIPTION
Outputs
tob
toen
todis
47 Output Buffer Delay
48 I/O Cell OE to Output Enabled
49 I/O Cell OE to Output Disabled
Clocks
tgy0
tgy1/2
tgcp
tioy2/3
tiocp
50 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
51 Clock Delay, Y1 or Y2 to Global GLB Clock Line
52 Clock Delay, Clock GLB to Global GLB Clock Line
53 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
54 Clock Delay, Clock GLB to I/O Cell Global Clock Line
Global Reset
tgr
55 Global Reset to GLB and I/O Registers
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
-90
-80
-60
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
– 2.4 – 3.0 – 4.0 ns
– 4.0 – 5.0 – 6.7 ns
– 4.0 – 5.0 – 6.7 ns
3.6 3.6 4.5 4.5 6.0 6.0 ns
2.8 4.4 3.5 5.5 4.6 7.3 ns
0.8 4.0 1.0 5.0 1.3 6.6 ns
2.8 4.4 3.5 5.5 4.6 7.3 ns
0.8 4.0 1.0 5.0 1.3 6.6 ns
– 8.2 – 9.0 – 12.0 ns
7
1996 ISP Encyclopedia