GAL22V10 Datasheet, PDF (17/29 Pages) Lattice Semiconductor – High Performance E2CMOS PLD Generic Array Logic

Specifications GAL22V10
Power-Up Reset
Vcc (min.)
Vcc
CLK
INTERNAL REGISTER
Q - OUTPUT
t su
t wl
t pr
Internal Register
Reset to Logic "0"
ACTIVE LOW
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
ACTIVE HIGH
OUTPUT REGISTER
Device Pin
Reset to Logic "0"
Circuitry within the GAL22V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1µs MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the asyn-
chronous nature of system power-up, some conditions must be
met to guarantee a valid power-up reset of the GAL22V10. First,
the Vcc rise must be monotonic. Second, the clock input must
be at static TTL level as shown in the diagram during power up.
The registers will reset within a maximum of tpr time. As in nor-
mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.
Input/Output Equivalent Schematics
PIN
(Vref Typical = 3.2V)
Vcc
Active Pull-up
Circuit
Vcc Vref Vcc
ESD
Protection
Circuit
PIN
Feedback
Tri-State
Control
Active Pull-up
Circuit
(Vref Typical = 3.2V)
Vcc
Vref
PIN
ESD
Protection
Circuit
Typical Input
Data
Output
PIN
Feedback
(To Input Buffer)
Typical Output
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