GAL22V10 Datasheet, PDF (10/29 Pages) Lattice Semiconductor – High Performance E2CMOS PLD Generic Array Logic

SpSepceifcicifaictaiotinosnsGGALA2L22V21V01C0
AC Switching Characteristics
Over Recommended Operating Conditions
COM
COM/IND COM/IND
COM
IND
TEST
PARAM _COND.1
DESCRIPTION
tpd
A Input or I/O to Combinatorial Output
-5
-7 (PLCC) -7 (PDIP)
-10
-10
UNITS
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
1 5 1 7.5 1 7.5 3 10 1 10 ns
tco
A Clock to Output Delay
1 4 1 4.5 1 4.5 2 7 1 7 ns
tcf²
— Clock to Feedback Delay
— 3 — 3 — 3 — 2.5 — 2.5 ns
tsu
— Setup Time, Input or Fdbk before Clk↑ 3 — 4.5 — 5 — 7 — 7 — ns
th
— Hold Time, Input or Fdbk after Clk↑
0 — 0 — 0 — 0 — 0 — ns
A Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
142.8 — 111 — 105 — 71.4 — 71.4 — MHz
fmax³
A Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
166 — 133 — 125 — 105 — 105 — MHz
A Maximum Clock Frequency with
No Feedback
200 — 166 — 142.8 — 105 — 105 — MHz
twh
twl
ten
tdis
tar
tarw
tarr
tspr
— Clock Pulse Duration, High
2.5 — 3 — 3.5 — 4 — 4 — ns
— Clock Pulse Duration, Low
2.5 — 3 — 3.5 — 4 — 4 — ns
B Input or I/O to Output Enabled
1 6 1 7.5 1 7.5 3 10 1 10 ns
C Input or I/O to Output Disabled
1 6 1 7.5 1 7.5 3 9 1 9 ns
A Input or I/O to Asynch. Reset of Reg. 1 5.5 1 9 1 9 3 13 1 13 ns
— Asynch. Reset Pulse Duration
5.5 — 7 — 7 — 8 — 8 — ns
— Asynch. Reset to Clk↑ Recovery Time 4 — 5 — 5 — 8 — 8 — ns
— Synch. Preset to Clk↑ Recovery Time 4 — 5 — 5 — 10 — 10 — ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section. Characterized initially and after any design or process changes that may affect these
parameters.
Capacitance (T_A = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
C_I
Input Capacitance
C_I/O
I/O Capacitance
*Characterized but not 100% tested.
MAXIMUM*
8
8
UNITS
pF
pF
TEST CONDITIONS
V_CC = 5.0V, V_I = 2.0V
V_CC = 5.0V, V_I/O = 2.0V
10