GAL22V10 Datasheet, PDF (12/29 Pages) Lattice Semiconductor – High Performance E2CMOS PLD Generic Array Logic

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Over Recommended Operating Conditions
COM
COM COM / IND
IND
COM / IND
PARAM.
TEST
COND.¹
DESCRIPTION
tpd
A Input or I/O to Comb. Output
-7
-10
-15
-20
-25
UNITS
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
3 7.5 3 10 3 15 3 20 3 25 ns
tco
A Clock to Output Delay
2 5 2 7 2 8 2 10 2 15 ns
tcf²
— Clock to Feedback Delay
— 2.5 — 2.5 — 2.5 — 8 — 13 ns
tsu₁
— Setup Time, Input or Fdbk before Clk↑ 6.5 — 7 — 10 — 14 — 15 — ns
tsu₂
— Setup Time, SP before Clock↑
10 — 10 — 10 — 14 — 15 — ns
th
— Hold Time, Input or Fdbk after Clk↑
0 — 0 — 0 — 0 — 0 — ns
A Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
87 — 71.4 — 55.5 — 41.6 — 33.3 — MHz
fmax³
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
111 — 105 — 80 — 45.4 — 35.7 — MHz
A Maximum Clock Frequency with
No Feedback
111 — 105 — 83.3 — 50 — 38.5 — MHz
twh
— Clock Pulse Duration, High
4 — 4 — 6 — 10 — 13 — ns
twl
— Clock Pulse Duration, Low
4 — 4 — 6 — 10 — 13 — ns
ten
B Input or I/O to Output Enabled
3 8 3 10 3 15 3 20 3 25 ns
tdis
C Input or I/O to Output Disabled
3 8 3 9 3 15 3 20 3 25 ns
tar
A Input or I/O to Asynch. Reset of Reg. 3 13 3 13 3 20 3 25 3 25 ns
tarw — Asynch. Reset Pulse Duration
8 — 8 — 15 — 20 — 25 — ns
tarr
— Asynch. Reset to Clk↑ Recovery Time 8 — 8 — 10 — 20 — 25 — ns
tspr
— Synch. Preset to Clk↑ Recovery Time 10 — 10 — 10 — 14 — 15 — ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
Capacitance (T_A = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
C
Input Capacitance
I
C_I/O
I/O Capacitance
*Characterized but not 100% tested.
MAXIMUM*
8
8
UNITS
pF
pF
TEST CONDITIONS
V = 5.0V, V = 2.0V
CC
I
V_CC = 5.0V, V_I/O = 2.0V
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