GAL22V10 Datasheet, PDF (15/29 Pages) Lattice Semiconductor – High Performance E2CMOS PLD Generic Array Logic

Switching Test Conditions
Input Pulse Levels
Input Rise and D-4/-5/-7, C-5
Fall Times
D-10/-15/-20/-25
B & C-7/-10
B-15/-20/-25 3ns
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
1.5ns 10% – 90%
2.0ns 10% – 90%
10% – 90%
1.5V
1.5V
See Figure
3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (except D-4) (see figure below)
Test Condition
R1
R2
CL
A
B Active High
Active Low
C Active High
Active Low
300Ω
∞
300Ω
∞
300Ω
390Ω
390Ω
390Ω
390Ω
390Ω
50pF
50pF
50pF
5pF
5pF
+5V
R1
Specifications GAL22V10
GAL22V10D-4 Output Load Conditions (see figure below)
Test Condition
R1
CL
A
50Ω
50pF
B Z to Active High at 1.9V
50Ω
50pF
Z to Active Low at 1.0V
50Ω
50pF
C Active High to Z at 1.9V
50Ω
50pF
Active Low to Z at 1.0V
50Ω
50pF
+1.45V
TEST POINT
R1
FROM OUTPUT (O/Q)
UNDER TEST
Z₀ = 50Ω, CL*
FROM OUTPUT (O/Q)
UNDER TEST
R2
TEST POINT
C _L*
*C _L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
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