GAL22V10 Datasheet, PDF(14/29 Page) Lattice Semiconductor – High Performance E2CMOS PLD Generic Array Logic

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GAL22V10 Datasheet, PDF (14/29 Pages) Lattice Semiconductor – High Performance E2CMOS PLD Generic Array Logic

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fmax Descriptions

CLK

LOGIC

ARRAY

ts u

tc o

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is cal-

culated from measured tsu and tco.

CLK

LOGIC

ARRAY

tsu + th

fmax with No Feedback

Note: fmax with no feedback may be less

than 1/(twh + twl). This is to allow for a

clock duty cycle of other than 50%.

Specifications GAL22V10

LOGIC

ARRAY

CLK

t cf

t pd

fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by sub-

tracting tsu from the period of fmax w/internal

feedback (tcf = 1/fmax - tsu). The value of tcf is

used primarily when calculating the delay from

clocking a register to a combinatorial output

(through registered feedback), as shown above.

For example, the timing from clock to a combi-

natorial output is equal to tcf + tpd.

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