1032EA Datasheet, PDF (14/16 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1032EA
Pin Description
NAME
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
TQFP PIN
NUMBERS
DESCRIPTION
17, 18, 19, 20, ^{Input/Output Pins - These are the general purpose I/O pins used by the logic array.}
21, 22, 23, 28,
29, 30, 31, 32,
33, 34, 35, 36,
40, 41, 42, 43,
44, 45, 46, 47,
48, 53, 54, 55,
56, 57, 58, 59,
67, 68, 69, 70,
71, 72, 73, 78,
79, 80, 81, 82,
83, 84, 85, 86,
90, 91, 92, 93,
94, 95, 96, 97,
98, 3, 4, 5,
6, 7, 8, 9
GOE 0/IN 4¹ 66
GOE 1/IN 5¹ ₈₇
This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be
used as a dedicated input pin.
This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be
used as a dedicated input pin.
IN 6, IN 7
89, 10
Dedicated input pins to the device.
TDI
16
TMS
37
TDO
39
TCK
60
RESET
15
Y0
11
Y1
65
Input - Functions as an input pin to load programming data into the device and also used as one of
the two control pins for the ispJTAG state machine.
Input - Controls the operation of the ISP state machine.
Output - Functions as an output pin to read serial shift register data.
Input - Functions as a clock pin for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on
the device.
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any GLB on the device.
Y2
62
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any GLB and/or any I/O cell on the device.
Y3
61
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any I/O cell on the device.
GND
VCC
13, 38, 63, 88 Ground (GND)
12, 64
Vcc
VCCIO
14
Supply voltage for output drivers, 5V or 3.3V.
NC²
1, 2, 24, 25, No connect.
26, 27, 49, 50,
51, 52, 74, 75,
76, 77, 99, 100
1. Pins have dual function capability which is software selectable.
2. NC pins are not to be connected to any active signals, Vcc or GND.
Table 2-0002A/1032EA
14