1032EA Datasheet, PDF (10/16 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1032EA
Internal Timing Parameters¹
PARAM. #²
DESCRIPTION
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
22 I/O Register Bypass
23 I/O Latch Delay
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
GRP
tgrp1 29 GRP Delay, 1 GLB Load
tgrp4 30 GRP Delay, 4 GLB Loads
tgrp8 31 GRP Delay, 8 GLB Loads
tgrp16 32 GRP Delay, 16 GLB Loads
tgrp32 33 GRP Delay, 32 GLB Loads
GLB
t4ptbpc 34 4 Product Term Bypass Path Delay (Combinatorial)
t4ptbpr 35 4 Product Term Bypass Path Delay (Registered)
t1ptxor 36 1 Product Term/XOR Path Delay
t20ptxor 37 20 Prod. Term/XOR Path Delay
txoradj 38 XOR Adjacent Path Delay ³
tgbp 39 GLB Register Bypass Delay
tgsu
tgh
40 GLB Register Setup Time before Clock
41 GLB Register Hold Time after Clock
tgco
42 GLB Register Clock to Output Delay
tgro
tptre
tptoe
tptck
43 GLB Register Reset to Output Delay
44 GLB Product Term Reset to Register Delay
45 GLB Product Term Output Enable to I/O Cell Delay
46 GLB Product Term Clock Delay
tgfb
47 GLB Feedback Delay
ORP
torp
torpbp
48 ORP Delay
49 ORP Bypass Delay
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
-125
-100
UNITS
MIN. MAX. MIN. MAX.
— 0.3 — 0.4 ns
— 4.0 — 4.0 ns
3.0 — 3.4 — ns
0.0 — 0.0 — ns
— 4.6 — 5.0 ns
— 4.6 — 5.0 ns
— 1.9 — 2.2 ns
— 1.7 — 2.1 ns
— 1.9 — 2.3 ns
— 2.1 — 2.5 ns
— 2.5 — 2.9 ns
— 3.3 — 3.7 ns
— 3.4 — 4.9 ns
— 3.1 — 3.8 ns
— 3.6 — 4.3 ns
— 3.6 — 4.3 ns
— 3.6 — 4.3 ns
— 1.2 — 2.1 ns
0.3 — 1.4 — ns
3.5 — 4.0 — ns
— 1.4 — 1.7 ns
— 4.9 — 5.0 ns
— 3.8 — 4.5 ns
— 5.7 — 7.2 ns
2.8 3.9 3.5 4.7 ns
— 0.3 — 0.3 ns
— 1.3
— 0.2
— 1.4 ns
— 0.4 ns
Table 2-0036B/1032EA
v.2.4
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