1032EA Datasheet, PDF (12/16 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1032EA
ispLSI 1032EA Timing Model
I/O Cell
GRP
GLB
#47
Feedback
Ded. In
I/O Pin
(Input)
#60
#28
I/O Reg Bypass
#22
Input
D ^Register Q
RST
#23 - 27
Reset
GRP4
#30
GRP Loading
Delay
#29, 31 - 33
#34 Comb 4 PT Bypass
Reg 4 PT Bypass
#35
20 PT
XOR Delays
#36 - 38
#60
GLB Reg Bypass
#39
GLB Reg
Delay
D
Q
RST
#40 - 43
ORP
I/O Cell
ORP Bypass
#49
ORP
Delay
#48
#50, 51
I/O Pin
(Output)
#52, 53
Y1,2,3
Clock
Distribution
#56 - 59
Control _RE
PTs _OE
#44 - 46 CK
#55
Y0
GOE 0,1
#54
Derivations of tsu, th and tco from the Product Term Clock¹
tsu
= Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min))
= (#22 + #30 + #37) + (#40) - (#22 + #30 + #46)
0.6 = (0.3 + 1.5 + 1.9) + (0.2) - (0.3 + 1.5 + 1.5)
th
= Clock (max) + Reg h - Logic
= (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
1.6 = (0.3 + 1.5 + 2.5) + (1.0) - (0.3 + 1.5 + 1.9)
tco
= Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
= (#22 + #30 + #46) + (#42) + (#48 + #50)
7.4 = (0.3 + 1.5 + 2.5) + (1.4) + (0.8 + 0.9)
Derivations of tsu, th and tco from the Clock GLB ¹
tsu
= Logic + Reg (setup) - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min))
= (#22 + #30 + #37) + (#40) - (#55 + #42 + #57)
0.8 = (0.3 + 1.5 + 1.9) + (0.2) - (0.9 + 1.4 + 0.8)
th
= Clock (max) + Reg (hold) - Logic
= (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#55 + #42 + #57) + (#41) - (#22 + #30 + #37)
1.4 = (0.9 + 1.4 + 1.8) + (1.0) - (0.3 + 1.5 + 1.9)
tco
= Clock (max) + Reg (clock-to-out) + Output
= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#55 + #42 + #57) + (#42) + (#48 + #50)
7.2 = (0.9 + 1.4 + 1.8) + (1.4) + (0.8 + 0.9)
1. Calculations are based upon timing specifications for the ispLSI 1032EA-200.
Table 2-0042a/1024EA
v.2.5
12
0491/1032EA