IS61NLP12832B Datasheet, PDF (7/29 Pages) Integrated Silicon Solution, Inc – 128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM

IS61NLP12832B
 IS61NLP12836B/IS61NVP12836B
 _{IS 61NLP25618A/IS61NVP25618A}
119-PIN PBGA PACKAGE CONFIGURATION 256K x 18 (TOP VIEW)
1
2
3
4
5
6
7
A
VDDQ
A
A
B
NC
CE2
A
NC
ADV
A
A
VDDQ
A
CE2
NC
C
NC
A
A
VDD
A
A
NC
D DQb
NC
VSS
NC
Vss
DQPa
NC
E
NC
DQb
VSS
CE
Vss
NC
DQa
F
VDDQ
NC
VSS
OE
Vss
DQa
VDDQ
G
NC
H DQb
J
VDDQ
K
NC
L _DQb
M
VDDQ
DQb
NC
VDD
DQb
NC
DQb
BWb
VSS
NC
VSS
NC
VSS
NC
WE
VDD
CLK
NC
CKE
NC
Vss
NC
Vss
BWa
Vss
NC
DQa
VDD
NC
DQa
NC
DQa
NC
VDDQ
DQa
NC
VDDQ
N DQb
NC
VSS
A1*
Vss
DQa
NC
P
NC
DQPb VSS
A0*
Vss
NC
DQa
R
NC
A
MODE VDD
NC
A
NC
T
NC
A
A
NC
A
A
ZZ
U VDDQ
NC
NC
NC
NC
NC
VDDQ
Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
WE
CLK
CKE
CE
CE2
CE2
BWx (x=a,b)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control
Input
Synchronous Clock
Clock Enable
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
Synchronous Byte Write Inputs
OE
ZZ
MODE
Vdd
Vss
NC
DQa-DQb
DQPa-Pb
Vddq
Output Enable
Power Sleep Mode
Burst Sequence Selection
Power Supply
Ground
No Connect
Data Inputs/Outputs
Parity Data I/O
Output Power Supply
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev.  D
09/10/07