IS61NLP12832B Datasheet, PDF (1/29 Pages) Integrated Silicon Solution, Inc – 128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM

IS61NLP12832B
IS61NLP12836B/IS61NVP12836B
 IS61NLP25618A/IS61NVP25618A
128K x 32, 128K x 36, and 256K x 18
4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
SEPTEMBER 2007
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control us-
ing MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 165-ball PBGA and 119-
ball PBGA packages
• Power supply:
NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%)
NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
• Industrial temperature available
• Lead-free available
FAST ACCESS TIME
Symbol
Parameter
-250
tkq
Clock Access Time
2.6
tkc
Cycle Time
4
Frequency
250
DESCRIPTION
The 4 Meg 'NLP/NVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 128K words by 32 bits, 128K words by 36
bits, and 256Kwords by 18 bits, fabricated with ISSI's
advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the ADV
input. When the ADV is HIGH the internal burst counter
is incremented. New external addresses can be loaded
when ADV is LOW.
Write cycles are internally self-timed and are initiated
by the rising edge of the clock inputs and when WE is
LOW. Separate byte enables allow individual bytes to be
written.
A burst mode pin (MODE) defines the order of the burst
sequence.When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
-200
3.1
5
200
Units
ns
ns
MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev.  D
09/10/07