IS61NLP12832B Datasheet, PDF (5/29 Pages) Integrated Silicon Solution, Inc – 128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM

IS61NLP12832B
 IS61NLP12836B/IS61NVP12836B
 _{IS 61NLP25618A/IS61NVP25618A}
119-PIN PBGA PACKAGE CONFIGURATION 128K x 36 (TOP VIEW)
1
2
3
4
5
6
7
A
VDDQ
A
A
B
NC
CE2
A
NC
ADV
A
A
VDDQ
A
CE2
NC
C
NC
A
A
VDD
A
A
NC
D DQc
E DQc
F
VDDQ
G DQc
H DQc
J
VDDQ
K _DQd
L _DQd
M
VDDQ
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
VSS
VSS
VSS
BWc
VSS
NC
VSS
BWd
VSS
NC
CE
OE
NC
WE
VDD
CLK
NC
CKE
Vss
Vss
Vss
BWb
Vss
NC
Vss
BWa
Vss
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
N DQd
DQd
VSS
A1*
Vss
DQa DQa
P ^DQd
DQPd
VSS
A0*
Vss DQPa DQa
R
NC
A
MODE
VDD
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U VDDQ
NC
NC
NC
NC
NC
VDDQ
Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
WE
CLK
CKE
CE
CE2
CE2
BWx (x=a-d)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control
Input
Synchronous Clock
Clock Enable
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
Synchronous Byte Write Inputs
OE
ZZ
MODE
Vdd
Vss
NC
DQa-DQd
DQPa-Pd
Vddq
Output Enable
Power Sleep Mode
Burst Sequence Selection
Power Supply
Ground
No Connect
Data Inputs/Outputs
Parity Data I/O
Output Power Supply
Integrated Silicon Solution, Inc. — www.issi.com
5
Rev.  D
09/10/07