X80140 Datasheet, PDF (9/18 Pages) Intersil Corporation – Voltage Supervisor/Sequencer Quad Programmable Time Delay with Local/Remote Voltage Monitors

X80140, X80141, X80142, X80143, X80144
Functional Description
Power On Reset and System Reset With Delay
Application of power to the X80140 activates a Power On
Reset circuit that pulls the RESET pin active. This signal, if
used, prevents the system microprocessor from starting to
operate while there is insufficient voltage on any of the
supplies. This circuit also does the following:
• It prevents the processor from operating prior to
stabilization of the oscillator.
• It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
• It prevents communication to the EEPROM during
unstable power conditions, greatly reducing the likelihood
of data corruption on power up.
• It allows time for all supplies to turn on and stabilize prior
to system initialization.
The POR/RESET circuit is activated when all voltages are
within specified ranges and the V1GDO, V2GDO, V3GDO,
and V4GDO time-out conditions are met. The POR/RESET
circuit will then wait t_SPOR and de-assert the RESET pin.
The POR delay may be changed by setting the TPOR bits in
register CR2. The delay can be set to 100ms, 500ms, 1
second, or 5 seconds.
TABLE 1. POR RESET DELAY OPTIONS
TPOR1 TPOR0
t_SPOR DELAY BEFORE RESET
ASSERTION
0
0
100 milliseconds (default)
0
1
500 milliseconds
1
0
1 second
1
1
5 seconds
Manual Reset
The manual reset option allows a hardware reset of the
power sequencing pins. These can be used to recover the
system in the event of an abnormal operating condition.
Activating the MR pin for more than 5us sets all of the
ViGDO outputs and the RESET output active (LOW). When
MR is released (and if all supplies are still at their proper
operating voltage) then the ViGDO and RESET pins will be
released after their programmed delay periods. (See Figure
3.)
Quad Voltage Monitoring
X80140 monitors 4 voltage inputs. When the ViMON (i=1-4)
input is detected to be above the input threshold, the output
ViGDO (i = 1 to 4) goes inactive (LOW). The ViGDO signal is
de-asserted after a delay of 100ms. This delay can be
changed on each ViGDO output individually with bits in
register CR3. The delay can be 100ms, 500ms, 1s and 5s.
Each ViGDO signal remains active until its associated
ViMON input rises above the threshold.
TABLE 2. VIGDO OUTPUT TIME DELAY OPTIONS
TiD1
0
TiD0
0
t_DELAYi
100ms (default)
0
1
500ms
1
0
1 secs
1
1
5 secs
where i is the specific voltage monitor (i = 1 to 4).
Fault Detection
The X80140 contains a Fault Detection Register (FDR) that
provides the user the status of the causes for a RESET pin
active (See Table 20).
At power-up, the FDR is defaulted to all “0”. The system
needs to initialize the register to 0Fh before the actual
monitoring can take place. In the event that any one of the
monitored sources fail, the corresponding bit in the register
changes from a “1” to a “0” to indicate the failure. When a
RESET is detected by the main controller, the controller
should read the FDR and note the cause of the fault. After
reading the register, the controller can reset the register bit
back to all “1” in preparation for future failure conditions.
Flexible Power Sequencing of Multiple Power
Supplies
The X80140 provides several circuits such as multiple
voltage monitors, programmable delays, and output drive
signals that can be used to set up flexible power monitoring
or sequencing schemes system power supplies. Below are
two examples:
1. Power Up of Supplies In Parallel Using Programmable
Delays. (See Figure 7 and Figure 8).
2. The X80140 monitors several power supplies, powered
by the same source voltage, that all begin power up at the
same time. Each voltage source is fed into the ViMON
inputs to the X80140. The ViMON inputs monitor the
voltage to make sure it has reached the minimum desired
level. When each voltage monitor determines that its
input is good, a counter starts. After the programmed
delay time, the X80140 sets the ViGDO signals LOW. Any
individual voltage failure can be viewed in the Fault
Detection Register.
3. In the factory default condition, each ViGDO output is
instructed to go LOW 100ms after the input voltage
reaches its threshold. However, each ViGDO delay is
individually selectable as 100ms, 500ms, 1s and 5s. The
delay times are changed via the SMBus during calibration
of the system.
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FN8153.0
January 20, 2005