X80140 Datasheet, PDF (8/18 Pages) Intersil Corporation – Voltage Supervisor/Sequencer Quad Programmable Time Delay with Local/Remote Voltage Monitors

X80140, X80141, X80142, X80143, X80144
Pin Configuration
X80140/1/2/3/4
V4GDO
V4MON
V3GDO
V3MON
V2GDO
20 19 18 17 16
1
15
2
14
3 ^{(5mm x 5mm)} ₁₃
4
12
5
11
6 7 8 9 10
WP
RESET
V1GDO
V1MON
SCL
Pin Descriptions
PIN
NAME
DESCRIPTION
1
V4GDO
V4 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V4MON is less than V_REF4
and goes LOW when V4MON is greater than V_REF4. There is user selectable delay circuitry on this pin.
2
V4MON
V4 Voltage Monitor Input. Fourth voltage monitor pin. If unused connect to V_CC.
3
V3GDO
V3 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V3MON is less than V_REF3
and goes LOW when V3MON is greater than V_REF3. There is user selectable delay circuitry on this pin.
4
V3MON
V3 Voltage Monitor Input. Third voltage monitor pin. If unused connect to V_CC.
5
V2GDO
V2 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V2MON is less than V_REF2
and goes LOW when V2MON is greater than V_REF2. There is user selectable delay circuitry on this pin.
6
V_P
EEPROM programming Voltage.
7
V2MON
V2 Voltage Monitor Input. Second voltage monitor pin. If unused connect to V_CC.
8
DNC
Do Not Connect.
9
A1
Address Select Input. It has an internal pull-down resistor. (>10MΩ typical)
The A0 and A1 bits allow for up to 4 X80140 devices to be used on the same SMBus serial interface.
10
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and
may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input
buffer is always active (not gated).
11
SCL
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
12
V1MON
V1 Voltage Monitor Input. First voltage monitor pin. If unused connect to V_CC.
13
V1GDO
V1 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V1MON is less than V_REF1
and goes LOW when V1MON is greater than V_REF1. There is user selectable delay circuitry on this pin.
14
RESET
RESET Output. This open drain pin is an active LOW output. This pin will be active until all ViGDO pins go inactive
and the power sequencing is complete. This pin will be released after a programmable delay.
15
WP
Write Protect. Input Pin. WP HIGH (in conjunction with WPEN bit=1) prevents writes to any memory location in the
device. It has an internal pull-down resistor. (>10MΩ typical)
16
MR
Manual Reset. Pulling the MR pin HIGH initiates a RESET. The MR signal must be held HIGH for 5µsecs. It has an
internal pull-down resistor. (>10MΩ typical)
17
V_SS
Ground Input.
18
NC
No Connect. No internal connections.
19
A0
Address Select Input. It has an internal pull-down resistor. (>10MΩ typical)
The A0 and A1 bits allow for up to 4 X80140 devices to be used on the same SMBus serial interface.
20
V_CC
Supply Voltage.
8
FN8153.0
January 20, 2005