X80140 Datasheet, PDF (16/18 Pages) Intersil Corporation – Voltage Supervisor/Sequencer Quad Programmable Time Delay with Local/Remote Voltage Monitors

X80140, X80141, X80142, X80143, X80144
master’s byte load operation, the device initiates the internal
high voltage cycle. Acknowledge polling can be initiated
immediately. To do this, the master issues a START
condition followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the high voltage
cycle then no ACK will be returned. If the device has
completed the write operation, an ACK will be returned and
the host can then proceed with the read or write operation.
See Figure 18.
Signals from
the Master
SDA Bus
S
t
a
Slave
r
Address
t
1010
0
Byte
Address
(1 to n to 16)
Data
(1)
S
Data
t
(n)
o
p
Signals from
the Slave
A
A
A
A
C
C
C
C
K
K
K
K
FIGURE 14. PAGE WRITE OPERATION
7 Bytes
5 Bytes
address
=6
address pointer
ends here
Addr = 7
address
10
address
n-1
FIGURE 15. WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 10
S
S
Signals from
the Master
t
Slave
a
r
Address
Byte
Address
t
Slave
a
Address
r
S
t
o
t
t
p
SDA Bus
101 0
0
101 0
1
Signals from
the Slave
A
A
C
C
K
K
A
C
K
Data
FIGURE 16. RANDOM ADDRESS READ SEQUENCE
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
Slave Address
a
r
t
S
t
o
p
101 0
1
A
C
K
Data
FIGURE 17. CURRENT ADDRESS READ SEQUENCE
16
FN8153.0
January 20, 2005