X80140 Datasheet, PDF (15/18 Pages) Intersil Corporation – Voltage Supervisor/Sequencer Quad Programmable Time Delay with Local/Remote Voltage Monitors

X80140, X80141, X80142, X80143, X80144
The Device Type Identifier MUST be set to 1010 in order
to select the device.
• The next two bits (SA3 - SA2) are slave address bits. The
bits received via the SMBus are compared to A0 and A1
pins and must match or the communication is aborted.
• The next bit, SA1, selects the device memory sector.
There are two addressable sectors: the memory array and
the control, fault detection and remote shutdown registers.
• The Least Significant Bit of the Slave Address (SA0) Byte
is the R/W bit. This bit defines the operation to be
performed. When the R/W bit is “1”, then a READ
operation is selected. A “0” selects a WRITE operation
(Refer to Figure 13).
DEVICE TYPE
IDENTIFIER
EXTERNAL
DEVICE
Memory _{READ /}
ADDRESS ^{Select WRITE}
SA7 SA6 SA5 SA4 SA3 SA2 _{SA1 SA0}
1
0
1
0
A1 A0 MS R/W
INTERNAL
ADDRESS (SA1)
0
1
INTERNALLY ADDRESSED
DEVICE
EEPROM Array
Control Register,
Fault Detection Register
BIT SA0
0
1
OPERATION
WRITE
READ
FIGURE 13. SLAVE ADDRESS FORMAT
Serial Write Operations
Before any write operations can be performed, a
programming supply voltage (V_P) must be supplied. This
voltage is only needed for programming, but the nonvolatile
registers and EEPROM locations cannot be programmed
without it.
In order to successfully complete a write operation to either a
Control Register or the EEPROM array, the Write Enable
Latch (WEL) bit must first be set and either the WP pin or the
WPEN bit must be LOW.
Writes to the WEL bit do not cause a high voltage write
cycle, so the device is ready for the next operation
immediately after the STOP condition.
BYTE WRITE
For a write operation, the device requires the Slave Address
Byte and a Word Address Byte. This gives the master
access to any one of the words in the array. After receipt of
the Word Address Byte, the device responds with an
acknowledge, and awaits the next eight bits of data. After
receiving the 8 bits of the Data Byte, the device again
responds with an acknowledge. The master then terminates
the transfer by generating a STOP condition, at which time
the device begins the internal write cycle to the nonvolatile
memory. During this internal write cycle, the device inputs
are disabled, so the device will not respond to any requests
from the master. The SDA output is at high impedance.
A write to a protected block of memory will suppress the
acknowledge bit.
PAGE WRITE
The device is capable of a page write operation. See Figure
14. It is initiated in the same manner as the byte write
operation; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit an
unlimited number of 8-bit bytes. After the receipt of each
byte, the device will respond with an acknowledge, and the
address is internally incremented by one. The page address
remains constant. When the counter reaches the end of the
page, it “rolls over” and goes back to ‘0’ on the same page.
See Figure 15.
This means that the master can write 16 bytes to the page
starting at any location on that page. If the master begins
writing at location 10, and loads 12 bytes, then the first 6
bytes are written to locations 10 through 15, and the last 6
bytes are written to locations 0 through 5. Afterwards, the
address counter would point to location 6 of the page that
was just written. If the master supplies more than 16 bytes of
data, then new data overwrites the previous data, one byte
at a time.
The master terminates the Data Byte loading by issuing a
STOP condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation, all
inputs are disabled until completion of the internal write
cycle.
STOP AND WRITE MODES
STOP conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte plus
the subsequent ACK signal. If a STOP is issued in the
middle of a data byte, or before 1 full data byte plus its
associated ACK is sent, then the device will reset itself
without performing the write. The contents of the array will
not be effected.
ACKNOWLEDGE POLLING
The disabling of the inputs during high voltage cycles can be
used to take advantage of the typical 5ms write cycle time.
Once the STOP condition is issued to indicate the end of the
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FN8153.0
January 20, 2005