X40030_13 Datasheet, PDF (9/23 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40030, X40031, X40034, X40035
The new V_TRIPX voltage to be applied to VXMON will now
be: V_TRIPX (desired) – (V_TRIPX (actual) – V_TRIPX (desired)).
Note: This operation does not corrupt the memory array.
Setting a Lower V_TRIPx Voltage (x=1, 2, 3)
In order to set V_TRIPx to a lower voltage than the present
value, then V_TRIPx must first be “reset” according to the
procedure described in the following. Once V_TRIPx has been
“reset”, then V_TRIPx can be set to the desired voltage using
the procedure described in “Setting a Higher VTRIPx
Voltage (x = 1, 2, 3)” on page 8.
Resetting the V_TRIPx Voltage
To reset a V_TRIPx voltage, apply the programming voltage
(Vp) to the WDO pin before a START condition is set up on
SDA. Next, issue on the SDA pin the Slave Address A0h
followed by the Byte Address 03h for V_TRIP1, 0Bh for V_TRIP2,
and 0Fh for V_TRIP3, followed by 00h for the Data Byte in
order to reset V_TRIPx. The STOP bit following a valid write
operation initiates the programming sequence. Pin WDO
must then be brought LOW to complete the operation.
After being reset, the value of V_TRIPx becomes a nominal
value of 1.7V or lesser.
Note: This operation does not corrupt the memory array.
Set V_CC ≅ 1.5(V2MON or V3MON), when setting V_TRIP2 or
V_TRIP3 respectively.
Control Register
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings. The
Block Lock and Watchdog Timer bits are nonvolatile and do
not change when power is removed.
The Control Register is accessed with a special preamble in
the slave byte (1011) and is located at address 1FFh. It can
only be modified by performing a byte write operation directly
to the address of the register and only one data byte is
allowed for each register write operation. Prior to writing to the
Control Register, the WEL and RWEL bits must be set using a
two step process, with the whole sequence requiring 3 steps.
See “Writing to the Control Registers” on page 11.
The user must issue a stop, after sending this byte to the
register, to initiate the nonvolatile cycle that stores WD1,
WD0, PUP1, PUP0 and BP. The X40030, X40031, X40034,
X40035 will not acknowledge any data bytes written after the
first byte is entered.
The state of the Control Register can be read at any time by
performing a random read at address 1FFh, using the
special preamble. Only one byte is read by each register
read operation. The master should supply a stop condition to
be consistent with the bus protocol.
7
6
5
4
PUP1 WD1 WD0 BP
3
2
1
0
0 RWEL WEL PUP0
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
V_TRIP1
ADJ.
V2FAIL
V_TRIP2
ADJ.
RESET
1
14
6
13
X40030
2
9
7
8
V_P
ADJUST
RUN
FIGURE 5. SAMPLE V_TRIP RESET CIRCUIT
µC
SCL
SDA
9
FN8114.2
August 25, 2008