X40030_13 Datasheet, PDF (14/23 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40030, X40031, X40034, X40035
S
S
SIGNALS
FROM THE
MASTER
T
SLAVE
A
R
ADDRESS
T
BYTE
ADDRESS
T
SLAVE
A _ADDRESS
R
T
S
T
O
P
SDA BUS
10 1 10 0 0 1 1 11 11 1 1
1
SIGNALS
FROM THE
SLAVE
A
A
C
C
K
K
A
C
K
DATA
FIGURE 11. RANDOM ADDRESS READ SEQUENCE
Read Operation
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master issues
the start condition and the Slave Address Byte, receives an
acknowledge, then issues the Word Address Bytes. After
acknowledging receipts of the Word Address Bytes, the
master immediately issues another start condition and the
Slave Address Byte with the R/W bit set to one. This is
followed by an acknowledge from the device and then by the
8-bit word. The master terminates the read operation by not
responding with an acknowledge and then issuing a stop
condition. See Figure 11 for the address, acknowledge, and
data transfer sequence.
Serial Device Addressing
Slave Address Byte
Following a start condition, the master must output a Slave
Address Byte. This byte consists of several parts:
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• The WEL bit must be set to allow write operations.
• The proper clock count and bit sequence is required prior
to the stop bit in order to start a nonvolatile write cycle.
• A three step sequence is required before writing into the
Control Register to change Watchdog Timer or Block Lock
settings.
• The WP pin, when held HIGH, prevents all writes to the
array and all the Register.
CONTROL REGISTER
FAULT DETECTION
REGISTER
SLAVE BYTE
1 0 1 1 0 0 1 R/W
1 0 1 1 0 0 0 R/W
CONTROL REGISTER
WORD ADDRESS
1 1 11 1 11 1
• a device type identifier that is always ‘1011’.
• 1-bit (AS) that provides the device select bit. AS bit is set to
“0” as factory default.
FAULT DETECTION
REGISTER
1 1 11 1 11 1
FIGURE 12. X40030, X40031, X40034, X40035 ADDRESSING
• next bit is ‘0’.
• last bit of the slave command byte is a R/W bit. The R/W
bit of the Slave Address Byte defines the operation to be
performed. When the R/W bit is a one, then a read
operation is selected. A zero selects a write operation.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter is
undefined on a power-up condition.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• The WEL bit is set to ‘0’. In this state it is not possible to
write to the device.
• SDA pin is the input mode.
• RESET/RESET Signal is active for t_PURST.
14
FN8114.2
August 25, 2008