X40030_13 Datasheet, PDF (13/23 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40030, X40031, X40034, X40035
SCL FROM
MASTER
1
DATA OUTPUT FROM
TRANSMITTER
8
9
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 9. ACKNOWLEDGE RESPONSE FROM RECEIVER
In the read mode, the device will transmit 8-bits of data,
release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will continue
to transmit data. The device will terminate further data
transmissions if an acknowledge is not detected. The master
must then issue a stop condition to return the device to
Standby mode and place the device into a known state.
Serial Write Operations
operation. If the device is still busy with the high voltage
cycle then no ACK will be returned. If the device has
completed the write operation, an ACK will be returned and
the host can then proceed with the read or write operation.
See Figure 10.
BYTE LOAD
COMPLETED BY
ISSUING STOP.
ENTER ACK POLLING
Byte Write
For a write operation, the device requires the Slave Address
Byte and a Word Address Byte. This gives the master access
to any one of the words in the array. After receipt of the Word
Address Byte, the device responds with an acknowledge, and
awaits the next eight bits of data. After receiving the 8 bits of
the Data Byte, the device again responds with an
acknowledge. The master then terminates the transfer by
generating a stop condition, at which time the device begins
the internal write cycle to the nonvolatile memory. During this
internal write cycle, the device inputs are disabled, so the
device will not respond to any requests from the master. The
SDA output is at high impedance. See Figure 10.
A write to a protected block of memory will suppress the
acknowledge bit.
ISSUE START
ISSUE SLAVE
ADDRESS BYTE
(READ OR WRITE)
ACK
RETURNED?
YES
ISSUE STOP
NO
HIGH VOLTAGE CYCLE
COMPLETE. CONTINUE
COMMAND SEQUENCE?
ISSUE STOP
NO
Stops and Write Modes
Stop conditions that terminate write operations must be sent
by the master after sending at least 1 full data byte plus the
subsequent ACK signal. If a stop is issued in the middle of a
data byte, or before 1 full data byte plus its associated ACK
is sent, then the device will reset itself without performing the
write. The contents of the array will not be effected.
YES
CONTINUE NORMAL
READ OR WRITE
COMMAND SEQUENCE
PROCEED
Acknowledge Polling
The disabling of the inputs during high voltage cycles can be
used to take advantage of the typical 5ms write cycle time.
Once the stop condition is issued to indicate the end of the
master’s byte load operation, the device initiates the internal
high voltage cycle. Acknowledge polling can be initiated
immediately. To do this, the master issues a start condition
followed by the Slave Address Byte for a write or read
FIGURE 10. ACKNOWLEDGE POLLING SEQUENCE
Serial Read Operations
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the Slave
Address Byte is set to one. There are three basic read
operations: Current Address Reads, Random Reads, and
Sequential Reads.
13
FN8114.2
August 25, 2008