X40030_13 Datasheet, PDF (12/23 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40030, X40031, X40034, X40035
MRF: Manual Reset Fail Bit (Volatile)
The MRF bit will be set to “0” when Manual Reset input goes
active.
WDF: Watchdog Timer Fail Bit (Volatile)
The WDF bit will be set to “0” when the WDO goes active.
LV1F: Low V_CC Reset Fail Bit (Volatile)
The LV1F bit will be set to “0” when V_CC (V1MON) falls
below V_TRIP1.
LV2F: Low V2MON Reset Fail Bit (Volatile)
The LV2F bit will be set to “0” when V2MON falls below
V_TRIP2.
LV3F: Low V3MON Reset Fail Bit (Volatile)
The LV3F bit will be set to “0” when the V3MON falls below
V_TRIP3.
Serial Interface
Interface Conventions
The device supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter, and the receiving device as the receiver. The
device controlling the transfer is called the master and the
device being controlled is called the slave. The master always
initiates data transfers, and provides the clock for both
transmit and receive operations. Therefore, the devices in this
family operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. See Figure 7.
Serial Start Condition
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met. See Figure 8.
Serial Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
condition can only be issued after the transmitting device
has released the bus. See Figure 8.
Serial Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting 8-bits.
During the ninth clock cycle, the receiver will pull the SDA
line LOW to acknowledge that it received the 8-bits of data.
See Figure 9.
The device will respond with an acknowledge after
recognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave Address
Byte. If a write operation is selected, the device will respond
with an acknowledge after the receipt of each subsequent
8-bit word. The device will acknowledge all incoming data
and address bytes, except for the Slave Address Byte when
the Device Identifier and/or Select bits are incorrect.
.
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 7. VALID DATA CHANGES ON THE SDA BUS
SCL
SDA
START
STOP
FIGURE 8. VALID START AND STOP CONDITIONS
12
FN8114.2
August 25, 2008