ISL78223 Datasheet, PDF (9/20 Pages) Intersil Corporation – ZVS Full-Bridge PWM Controller with Adjustable Synchronous Rectifier Control

ISL78223
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2
and “Typical Application” schematics beginning on page 3. 9V < V_DD < 20V, RTD = 10.0kΩ, CT = 470pF, T_A = -40°C to +105°C, Typical values are at
T_A = +25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 11)
TYP
(Note 11) UNITS
SOFT-START
Charging Current (Sourcing)
SS = 3V
55
70
81
µA
SS Clamp Voltage
4.4
4.500
4.65
V
SS Discharge Current
SS = 2V
10
30
-
mA
Reset Threshold Voltage
OUTPUT
T_A = +25°C
0.23
0.27
0.33
V
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Rise Time
Fall Time
UVLO Output Voltage Clamp
Output Delay/Advance Range
OUTLLN/OUTLRN Relative to OUTLL/OUTLR
Delay/Advance Control Voltage Range
OUTLLN/OUTLRN Relative to OUTLL/OUTLR
I_OUT = 10mA, V_DD - VOH
I_OUT = -10mA, VOL - GND
C_OUT = 220pF, V_DD = 15V (Note 7)
C_OUT = 220pF, V_DD = 15V (Note 7)
V_DD = 7V, I_LOAD = 1mA (Note 9)
V_ADJ = 2.50V (Note 7)
V_ADJ < 2.425V (Note 7)
V_ADJ > 2.575V (Note 7)
OUTLxN Delayed (Note 7)
OUTLxN Advanced (Note 7)
-
0.5
1.0
V
-
0.3
1.0
V
-
110
200
ns
-
90
150
ns
-
-
1.25
V
-
2
-
ns
-40
-
-300
ns
40
-
300
ns
2.575
-
5.000
V
0
-
2.425
V
V_ADJ Delay Time
THERMAL PROTECTION
T_A = +25°C (OUTLx Delayed) (Note 10)
V_ADJ = 0
V_ADJ = 0.5V
V_ADJ = 1.0V
V_ADJ = 1.5V
V_ADJ = 2.0V
T_A = +25°C (OUTLxN Delayed)
V_ADJ = V_REF
V_ADJ = V_REF - 0.5V
V_ADJ = V_REF - 1.0V
V_ADJ = V_REF - 1.5V
V_ADJ = V_REF - 2.0V
-
300
-
ns
-
105
-
ns
-
70
-
ns
-
55
-
ns
-
50
-
ns
-
300
-
ns
-
100
-
ns
-
68
-
ns
-
55
-
ns
-
48
-
ns
Thermal Shutdown
(Note 7)
-
140
-
°C
Thermal Shutdown Clear
(Note 7)
-
125
-
°C
Hysteresis, Internal Protection
(Note 7)
-
15
-
°C
NOTES:
7. Limits established by characterization and are not production tested.
8. This is the maximum duty cycle achievable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may be obtained using
other values for these components. See Equations 1 through 3.
9. Adjust V_DD below the UVLO stop threshold prior to setting at 7V.
10. When OUTLx is delayed relative to OUTLxN (V_ADJ < 2.425V), the delay duration as set by V_ADJ should not exceed 90% of the CT discharge time
(deadtime) as determined by CT and RTD.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9
FN7936.1
January 2, 2013