ISL78223 Datasheet, PDF (16/20 Pages) Intersil Corporation – ZVS Full-Bridge PWM Controller with Adjustable Synchronous Rectifier Control

ISL78223
CT
DEADTIME
OUTLL
OUTLR
PWM
PWM
PWM
PWM
OUTUR
RESONANT
DELAY
OUTUL
RESDEL
WINDOW
FIGURE 14. BRIDGE DRIVE SIGNAL TIMING
To understand how the ZVS method operates, one must include
the parasitic elements of the circuit and examine a full switching
cycle.
VIN+
UL
UR
D1
L_L
VOUT+
RTN
LL
LR
D2
VIN-
FIGURE 15. IDEALIZED FULL-BRIDGE
In Figure 15, the power semiconductor switches have been
replaced by ideal switch elements with parallel diodes and
capacitance, the output rectifiers are ideal, and the transformer
leakage inductance has been included as a discrete element.
The parasitic capacitance has been lumped together as switch
capacitance, but represents all parasitic capacitance in the
circuit including winding capacitance. Each switch is designated
by its position, upper left (UL), upper right (UR), lower left (LL),
and lower right (LR). The beginning of the cycle, shown in
Figure 16, is arbitrarily set as having switches UL and LR on and
UR and LL off. The direction of the primary and secondary
currents are indicated by I_P and I_S, respectively.
VIN+
UL
I_P
UR
L_L
D1
I_S
VOUT+
RTN
LL
LR
D2
VIN-
FIGURE 16. UL - LR POWER TRANSFER CYCLE
The UL - LR power transfer period terminates when switch LR
turns off as determined by the PWM. The current flowing in the
primary cannot be interrupted instantaneously, so it must find an
alternate path. The current flows into the parasitic switch
capacitance of LR and UR which charges the node to VIN and
then forward biases the body diode of upper switch UR.
VIN+
UL
I_P
LL
UR
L_L
LR
D1
I_S
D2
VOUT+
RTN
VIN-
FIGURE 17. UL - UR FREE-WHEELING PERIOD
The primary leakage inductance, L_L, maintains the current which
now circulates around the path of switch UL, the transformer
primary, and switch UR. When switch LR opens, the output
inductor current free-wheels through both output diodes, D1 and
D2. During the switch transition, the output inductor current
assists the leakage inductance in charging the upper and lower
bridge FET capacitance.
The current flow from the previous power transfer cycle tends to
be maintained during the free-wheeling period because the
transformer primary winding is essentially shorted. Diode D1
may conduct very little or none of the free-wheeling current,
depending on circuit parasitics. This behavior is quite different
than what occurs in a conventional hard-switched full-bridge
topology where the free-wheeling current splits nearly evenly
between the output diodes, and flows not at all in the primary.
This condition persists through the remainder of the half-cycle.
During the period when CT discharges, also referred to as the
deadtime, the upper switches toggle. Switch UL turns off and
switch UR turns on. The actual timing of the upper switch toggle
is dependent on RESDEL which sets the resonant delay. The
voltage applied to RESDEL determines how far in advance the
toggle occurs prior to a lower switch turning on. The ZVS
transition occurs after the upper switches toggle and before the
diagonal lower switch turns on. The required resonant delay is
1/4 of the period of the LC resonant frequency of the circuit
formed by the leakage inductance and the parasitic capacitance.
The resonant transition may be estimated from Equation 27.
τ
=
-^π- -----------------¹------------------
2 _{------1-------- – --R----2---}
L_LC_{P 4LL2}
(EQ. 27)
where τ is the resonant transition time, L_L is the leakage
inductance, C_P is the parasitic capacitance, and R is the
equivalent resistance in series with L_L and C_P.
The resonant delay is always less than or equal to the deadtime
and may be calculated using Equation 28.
τ_resdel
=
-^V----^r--^e---^s---^d----^e--^l ⋅ DT
2
S
(EQ. 28)
where τ_resdel is the desired resonant delay, V_resdel is a voltage
between 0V and 2V applied to the RESDEL pin, and DT is the
deadtime (see Equations 1 through 5).
16
FN7936.1
January 2, 2013