ISL78223 Datasheet, PDF (18/20 Pages) Intersil Corporation – ZVS Full-Bridge PWM Controller with Adjustable Synchronous Rectifier Control

ISL78223
CT
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
CT
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
FIGURE 22. BASIC WAVEFORM TIMING
Referring to Figure 22, the SRs alternate between being both on
during the free-wheeling portion of the cycle (OUTLL/LR off), and
one or the other being off when OUTLL or OUTLR is on. If OUTLL is
on, its corresponding SR must also be on, indicating that OUTLRN
is the correct SR control signal. Likewise, if OUTLR is on, its
corresponding SR must also be on, indicating that OUTLLN is the
correct SR control signal.
A useful feature of the ISL78223 is the ability to vary the phase
relationship between the PWM outputs (OUTLL, OUT LR) and the
their complements (OUTLLN, OUTLRN) by ±300ns. This feature
allows the designer to compensate for differences in the
propagation times between the PWM FETs and the SR FETs. A
voltage applied to V_ADJ controls the phase relationship.
CT
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
FIGURE 23. WAVEFORM TIMING WITH PWM OUTPUTS DELAYED,
0V < V_ADJ < 2.425V
FIGURE 24. WAVEFORM TIMING WITH SR OUTPUTS DELAYED,
2.575V < V_ADJ < 5.00V
Setting V_ADJ to V_REF/2 results in no delay on any output. The no
delay voltage has a ±75mV tolerance window. Control voltages
below the V_REF/2 zero delay threshold cause the PWM outputs,
OUTLL/LR, to be delayed. Control voltages greater than the
V_REF/2 zero delay threshold cause the SR outputs, OUTLLN/LRN,
to be delayed. It should be noted that when the PWM outputs,
OUTLL/LR, are delayed, the CS to output propagation delay is
increased by the amount of the added delay.
The delay feature is provided to compensate for mismatched
propagation delays between the PWM and SR outputs as may be
experienced when one set of signals crosses the
primary-secondary isolation boundary. If required, individual
output pulses may be stretched or compressed as required using
external resistors, capacitors, and diodes.
When the PWM outputs are delayed, the 50% upper outputs are
equally delayed, so the resonant delay setting is unaffected.
On/Off Control
The ISL78223 does not have a separate enable/disable control
pin. The PWM outputs, OUTLL/OUTLR, may be disabled by pulling
VERR to ground. Doing so reduces the duty cycle to zero, but the
upper 50% duty cycle outputs, OUTUL/OUTUR, will continue
operation. Likewise, the SR outputs OUTLLN/OUTLRN will be
active high.
Pulling Soft-Start to ground will disable all outputs and set them
to a low condition.
Fault Conditions
A fault condition occurs if V_REF or V_DD fall below their
undervoltage lockout (UVLO) thresholds or if the thermal
protection is triggered. When a fault is detected the outputs are
disabled low. When the fault condition clears the outputs are
re-enabled.
An overcurrent condition is not considered a fault and does not
result in a shutdown.
18
FN7936.1
January 2, 2013